A curve fitting approach for non-iterative divider design with accuracy and performance trade-off

This paper presents an approach based on the curve fitting method for the design of non-iterative divider circuits with accuracy and area-delay product (ADP) trade-offs. The curved surfaces representing the quotient are partitioned into several regions, each of which is then approximated by a square/triangular plane. The planes are obtained by using the curve fitting method for accuracy optimization. The proposed architecture for implementing the planes contains only simple arithmetic operations and a look-up table. Several non-iterative divider circuits with different accuracies and ADPs are obtained. The accuracy achieved in terms of the maximum absolute error percentage (MAEP) ranges from 1.87% to 0.14%. The MAEP of 0.14% is 30% better than the one achieved by the best existing non-iterative divider.

[1]  Ching-Chuen Jong,et al.  Non-iterative high speed division computation based on Mitchell logarithmic method , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[2]  John N. Mitchell,et al.  Computer Multiplication and Division Using Binary Logarithms , 1962, IRE Trans. Electron. Comput..

[3]  Jin-Yong Chung,et al.  A 210mW graphics LSI implementing full 3D pipeline with 264Mtexels/s texturing for mobile multimedia applications , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[4]  Sanu Mathew,et al.  A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS , 2013, IEEE Journal of Solid-State Circuits.

[5]  Hoi-Jun Yoo,et al.  A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System , 2005, IEEE Journal of Solid-State Circuits.

[6]  Bogdan Pasca.  Correctly rounded floating-point division for DSP-enabled FPGAs , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

[7]  Hoi-Jun Yoo,et al.  A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications , 2004, IEEE Journal of Solid-State Circuits.

[8]  M. Ercegovac,et al.  Division and Square Root: Digit-Recurrence Algorithms and Implementations , 1994 .

[9]  T. Sato,et al.  2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing , 2000, IEEE Journal of Solid-State Circuits.

[10]  Michael J. Flynn.  On Division by Functional Iteration , 1970, IEEE Transactions on Computers.

[11]  Ching-Chuen Jong,et al.  Unified Mitchell-Based Approximation for Efficient Logarithmic Conversion Circuit , 2015, IEEE Transactions on Computers.

[12]  T. Sakamoto,et al.  A 3D graphics library for 32-bit microprocessors for embedded systems , 1998 .

[13]  Michael J. Flynn,et al.  Division Algorithms and Implementations , 1997, IEEE Trans. Computers.