Effect of Interrupt Logic on Delay Balancing Circuit
暂无分享,去创建一个
[1] W. Liu,et al. Wave-pipelining: a tutorial and research survey , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[2] Manoj Sachdev,et al. A digitally programmable delay element: design and analysis , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[3] N. S. Kumar,et al. A New Method to Enhance Performance of Digital Frequency Measurement and Minimize the Clock Skew , 2011, IEEE Sensors Journal.
[4] Stephen H. Unger,et al. Clocking Schemes for High-Speed Digital Systems , 1986, IEEE Transactions on Computers.
[5] Wentai Liu,et al. Timing constraints for wave-pipelined systems , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] Narayanan Vijaykrishnan,et al. A clock power model to evaluate impact of architectural and technology optimizations , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[7] Jabulani Nyathi,et al. A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks , 2003, 2003 46th Midwest Symposium on Circuits and Systems.
[8] Eby G. Friedman,et al. Clock distribution networks in synchronous digital integrated circuits , 2001, Proc. IEEE.
[9] T. N. Prabakar,et al. Design and implementation of an Asynchronous Controller for FPGA Based Asynchronous Systems , 2010 .
[10] M.A. Horowitz,et al. Skew-tolerant domino circuits , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
[11] O. Takahashi,et al. A 1.0 GHz single-issue 64 b powerPC integer processor , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).