A Programmable Video DSP Architecture for HDTV Applications

[1]  Yutaka Takahashi,et al.  SVP: serial video processor , 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

[2]  Yoshihiro Fujita,et al.  A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM , 1994, IEEE J. Solid State Circuits.

[3]  T. Yamazaki,et al.  5.4 GOPS linear array architecture DSP for video-format conversion , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.