A fast and well-structured multiplier

The performance of multiplication is crucial for multimedia applications such as 3D graphics and signal processing systems which depend on extensive numbers of multiplications. Previously reported multiplication algorithms mainly focus on rapidly reducing the partial products rows down to final sums and carries used for the final accumulation. These techniques mostly rely on circuit optimization and minimization of the critical paths. In this paper, an algorithm to achieve fast multiplication in two's complement representation is presented. Indeed, our approach focuses on reducing the number of partial product rows. In turn, this directly influences the speed of the multiplication, even before applying partial products reduction techniques. Fewer partial products rows are produced, thereby lowering the overall operation time. This results in a true diamond-shape for the partial product tree which is more efficient in terms of implementation.

[1]  Reza Hashemian,et al.  A new parallel technique for design of decrement/increment and two's complement circuits , 1991, [1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems.

[2]  A 15 ns 32×32-bit CMOS multiplier with an improved parallel structure , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[3]  O. L. Macsorley.  High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.

[4]  Chein-Wei Jen,et al.  High-Speed Booth Encoded Parallel Multiplier Design , 2000, IEEE Trans. Computers.

[5]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[6]  Dharma P. Agrawal,et al.  On Multiple Operand Addition of Signed Binary Numbers , 1978, IEEE Transactions on Computers.

[7]  Alan Jay Smith,et al.  Measuring the Performance of Multimedia Instruction Sets , 2002, IEEE Trans. Computers.

[8]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[9]  F. Elguibaly,et al.  A fast parallel multiplier-accumulator using the modified Booth algorithm , 2000 .

[10]  Milos D. Ercegovac,et al.  High-performance left-to-right array multiplier design , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[11]  H. Makino,et al.  A 600-MHz 54/spl times/54-bit multiplier with rectangular-styled Wallace tree , 2001 .

[12]  Jalil Fadavi-Ardekani,et al.  M*N Booth encoded multiplier generator using optimized Wallace trees , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[13]  D. H. Jacobsohn,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[14]  한탁돈,et al.  4-2 콤프레서를 이용한 승산기 모듈 생성기의 설계 ( A Design of a Multiplier Modele Generator using 4-2 Compressor ) , 1993 .

[15]  R. Ravi,et al.  Optimal Circuits for Parallel Multipliers , 1998, IEEE Trans. Computers.

[16]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[17]  Vojin G. Oklobdzija,et al.  General data-path organization of a MAC unit for VLSI implementation of DSP processors , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[18]  Mark Horowitz,et al.  SPIM: a pipelined 64*64-bit iterative multiplier , 1989 .

[19]  Vojin G. Oklobdzija,et al.  Analysis of Booth encoding efficiency in parallel multipliers using compressors for reduction of partial products , 1993, Proceedings of 27th Asilomar Conference on Signals, Systems and Computers.

[20]  Vojin G. Oklobdzija,et al.  A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach , 1996, IEEE Trans. Computers.

[21]  Daniel D. Gajski.  Principles of Digital Design , 1996 .