In this paper, we described on the design and implementation of an ATM cell controller for a high speed interface between FRIM (Frame Relay Interworking Module) and ALS (ATM Local switching Subsystem). In upstream direction, the ATM cell controller receives a cell stream from 16 Frame Relay subscriber access boards, and performs UPC (Usage Parameter Control), cell head translation, EHEC generation, AAL type 5 segmentation, and ATM switch interface function. In reverse direction, the ATM cell controller classifies the received cell stream through an ATM switch into user cells and IPC (Inter Processor Communication) cells, and performs 64/53 octets conversion, AAL type 5 cell reassembly, HEC generation, and handling of user cells, IPC cells, and OAM cells. And these functions are implemented by using FPGA, and we have verified the whole ATM cell controller functions by connecting protocol tester, Frame Relay subscriber board and an ATM switch.