A test structure for statistical evaluation of pn junction leakage current based on CMOS image sensor technology

We propose a test structure to enable us to evaluate statistical distributions of small pn junction leakage currents of numerous samples in a very short time (0.1 – 10 fA, 28,672 n+/p diodes in 0.77s). This test structure is based on a CMOS active pixel image sensor, which contains a current-to-voltage conversion function by a capacitor and amplifiers of voltage signals in each pixel. The test structure can be designed easily because of a small number of mask layer requirements (at least one metal layer). Its simplicity has considerable benefits such as an easy fabrication for various processes without exceptional cares and also produces usefulness of statistical evaluation for anomalous pn junction leakage phenomena such as extremely large currents or dynamic and quantum fluctuations which show more and more as the device dimension shrinks.

[1]  Hyuck In Kwon,et al.  The analysis of dark signals in the CMOS APS imagers from the characterization of test structures , 2004, IEEE Transactions on Electron Devices.

[2]  Rita Rooyackers,et al.  Shallow trench isolation dimensions effects on leakage current and doping concentration of advanced p–n junction diodes , 2004 .

[3]  Tadahiro Ohmi,et al.  New Statistical Evaluation Method for the Variation of Metal–Oxide–Semiconductor Field-Effect Transistors , 2007 .

[4]  S. Sugawa,et al.  Statistical evaluation for anomalous SILC of tunnel oxide using integrated array TEG , 2008, 2008 IEEE International Reliability Physics Symposium.

[5]  K. Ohyu,et al.  Quantitative identification for the physical origin of variable retention time: A vacancy-oxygen complex defect model , 2006, 2006 International Electron Devices Meeting.

[6]  D. Yaney,et al.  A meta-stable leakage phenomenon in DRAM charge storage —Variable hold time , 1987, 1987 International Electron Devices Meeting.

[7]  S. Sugawa,et al.  Random Telegraph Signal Statistical Analysis using a Very Large-scale Array TEG with 1M MOSFETs , 2007, 2007 IEEE Symposium on VLSI Technology.

[8]  A. Theuwissen,et al.  Leakage current modeling of test structures for characterization of dark current in CMOS image sensors , 2003 .

[9]  Tadahiro Ohmi,et al.  Stress-induced leakage current and random telegraph signal , 2009 .

[10]  A. Teramoto,et al.  A Test Structure for Statistical Evaluation of Characteristics Variability in a Very Large Number of MOSFETs , 2009, 2009 IEEE International Conference on Microelectronic Test Structures.

[11]  A. Teramoto,et al.  Accurate Time Constant of Random Telegraph Signal Extracted by a Sufficient Long Time Measurement in Very Large-Scale Array TEG , 2009, 2009 IEEE International Conference on Microelectronic Test Structures.

[12]  Y. Mori,et al.  The origin of variable retention time in DRAM , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[13]  S. S. Park,et al.  The analysis of dark signals in the CMOS APS imagers from the characterization of test structures , 2004 .

[14]  J. Vallerga,et al.  Counting of deep-level traps using a charge-coupled device , 1987, IEEE Transactions on Electron Devices.

[15]  Tadahiro Ohmi,et al.  Anomalous Random Telegraph Signal Extractions from a Very Large Number of n-Metal Oxide Semiconductor Field-Effect Transistors Using Test Element Groups with 0.47 Hz–3.0 MHz Sampling Frequency , 2009 .

[16]  Tadahiro Ohmi,et al.  Asymmetry of RTS characteristics along source-drain direction and statistical analysis of process-induced RTS , 2009, 2009 IEEE International Reliability Physics Symposium.

[17]  A. Hiraiwa,et al.  Statistical modeling of dynamic random access memory data retention characteristics , 1996 .

[18]  T. Hamamoto,et al.  On the retention time distribution of dynamic random access memory (DRAM) , 1998 .

[19]  Eric R. Fossum,et al.  CMOS image sensors: electronic camera-on-a-chip , 1997 .

[20]  Jeong-Mo Hwang,et al.  Accurate extraction of reverse leakage current components of shallow silicided p/sup +/-n junction for quarter- and sub-quarter-micron MOSFET's , 1998 .

[21]  K. Yamaguchi Theoretical study of deep-trap-assisted anomalous currents in worst-bit cells of dynamic random-access memories (DRAM's) , 2000 .