论文信息 - Technologies for low latency interconnection switches

Technologies for low latency interconnection switches

This paper presents an engineering design for a low latency high bandwidth interconnection network which will form the switching substrate for a multi-model parallel processing system. The performance is enhanced with a variety of approaches covering interconnection protocols, routing, fault tolerance, advanced packaging, and electrical interconnection techniques. The synergistic application of these technologies leads to a high performance design.

Thomas F. Knight | T. Knight

[1] Charles L. Seitz,et al. The cosmic cube , 1985, CACM.

[2] W. Daniel Hillis,et al. The connection machine , 1985 .

[3] Kevin P. McAuliffe,et al. The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture , 1985, ICPP.

[4] Andreas Nowatzyk,et al. Coherent shared memory on a message passing machine , 1988 .

[5] W. J. Dally,et al. Finite-grain message passing concurrent computers , 1988, C3P.

[6] Thomas F. Knight,et al. Routing Statistics for Unqueued Banyan Networks , 1990 .

[7] R. Grondalski,et al. A VLSI chip set for a massively parallel architecture , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8] T. F. Knight,et al. A self-terminating low-voltage swing CMOS output driver , 1988 .

[9] Charles E. Leiserson,et al. Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.