Validation Techniques for Fault Emulation of SRAM-based FPGAs

A variety of fault emulation systems have been created to study the effect of single-event effects (SEEs) in static random access memory (SRAM) based field-programmable gate arrays (FPGAs). These systems are useful for augmenting radiation-hardness assurance (RHA) methodologies for verifying the effectiveness for mitigation techniques; understanding error signatures and failure modes in FPGAs; and failure rate estimation. For radiation effects researchers, it is important that these systems properly emulate how SEEs manifest in FPGAs. If the fault emulation systems does not mimic the radiation environment, the system will generate erroneous data and incorrect predictions of behavior of the FPGA in a radiation environment. Validation determines whether the emulated faults are reasonable analogs to the radiation-induced faults. In this paper we present methods for validating fault emulation systems and provide several examples of validated FPGA fault emulation systems.

[1]  Jeong-A Lee,et al.  A Low-Overhead Multiple-SEU Mitigation Approach for SRAM-based FPGAs with Increased Reliability , 2014, IEEE Transactions on Nuclear Science.

[2]  Mengu Cho,et al.  Evaluation of SRAM based FPGA performance by simulating SEU through fault injection , 2013, 2013 6th International Conference on Recent Advances in Space Technologies (RAST).

[3]  C. Lopez-Ongil,et al.  A Unified Environment for Fault Injection at Any Design Level Based on Emulation , 2007, IEEE Transactions on Nuclear Science.

[4]  Massimo Violante,et al.  An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits , 2002, J. Electron. Test..

[5]  C. Carmichael,et al.  Single Event Upsets in Xilinx Virtex-4 FPGA Devices , 2006, 2006 IEEE Radiation Effects Data Workshop.

[6]  John A. Clark,et al.  Efficient Software Verification: Statistical Testing Using Automated Search , 2010, IEEE Transactions on Software Engineering.

[7]  Mark E. Dunham,et al.  Space-Based FPGA Radio Receiver Design, Debug, and Development of a Radiation-Tolerant Computing System , 2010, Int. J. Reconfigurable Comput..

[8]  Darrel E. Johnson,et al.  Estimating the Dynamic Sensitive Cross Section of an FPGA Design through Fault injection , 2005 .

[9]  C. Carmichael,et al.  Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs) , 2004, IEEE Transactions on Nuclear Science.

[10]  Mário Zenha Rela,et al.  Evaluating Xilinx SEU Controller Macro for fault injection , 2013, 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN).

[11]  Oana Boncalo,et al.  Cost effective FPGA probabilistic fault emulation , 2014, 2014 NORCHIP.

[12]  Mario García-Valderas,et al.  Techniques for fast transient fault grading based on autonomous emulation [IC fault tolerance evaluation] , 2005, Design, Automation and Test in Europe.

[13]  Heather Quinn.  Challenges in Testing Complex Systems , 2014, IEEE Transactions on Nuclear Science.

[14]  Hong Zhu,et al.  Software unit test coverage and adequacy , 1997, ACM Comput. Surv..

[15]  Raoul Velazco,et al.  An Automated SEU Fault-Injection Method and Tool for HDL-Based Designs , 2013, IEEE Transactions on Nuclear Science.

[16]  Wolfram Burgard,et al.  Identification of critical variables using an FPGA-based fault injection framework , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[17]  Gary Swift,et al.  Single-Event Characterization of the 28 nm Xilinx Kintex-7 Field-Programmable Gate Array under Heavy Ion Irradiation , 2014, 2014 IEEE Radiation Effects Data Workshop (REDW).

[18]  Domenico Cotroneo,et al.  On Fault Representativeness of Software Fault Injection , 2013, IEEE Transactions on Software Engineering.

[19]  L. Sterpone,et al.  A New Partial Reconfiguration-Based Fault-Injection System to Evaluate SEU Effects in SRAM-Based FPGAs , 2007, IEEE Transactions on Nuclear Science.

[20]  Heather Quinn,et al.  Flight Experience of the Xilinx Virtex-4 , 2013, IEEE Transactions on Nuclear Science.

[21]  Seyed Ghassem Miremadi,et al.  SCFIT: A FPGA-based fault injection technique for SEU fault model , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[22]  M.A. Aguirre,et al.  A New Approach to Estimate the Effect of Single Event Transients in Complex Circuits , 2007, IEEE Transactions on Nuclear Science.

[23]  Sergio D'Angelo,et al.  Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[24]  Antonio Torralba,et al.  UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware Debugging , 2003, FPL.

[25]  Seyed Ghassem Miremadi,et al.  Fault injection into SRAM-based FPGAs for the analysis of SEU effects , 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

[26]  Nuno Laranjeiro,et al.  A Technique for Deploying Robust Web Services , 2014, IEEE Transactions on Services Computing.

[27]  Régis Leveugle,et al.  Pattern-based injections in processors implemented on SRAM-based FPGAs , 2012, 2012 13th Latin American Test Workshop (LATW).

[28]  Paolo Rech,et al.  Neutron Cross-Section of N-Modular Redundancy Technique in SRAM-Based FPGAs , 2014, IEEE Transactions on Nuclear Science.

[29]  Mario García-Valderas,et al.  Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures , 2011, IEEE Transactions on Dependable and Secure Computing.

[30]  Michael J. Wirthlin,et al.  The Cibola Flight Experiment , 2015, TRETS.

[31]  J. N. Tombs,et al.  Noninvasive Fault Classification, Robustness and Recovery Time Measurement in Microprocessor-Type Architectures Subjected to Radiation-Induced Errors , 2009, IEEE Transactions on Instrumentation and Measurement.

[32]  Paul Graham,et al.  Accelerator validation of an FPGA SEU simulator , 2003 .

[33]  J.N. Tombs,et al.  Radiation Environment Emulation for VLSI Designs: A Low Cost Platform based on Xilinx FPGA's , 2007, 2007 IEEE International Symposium on Industrial Electronics.

[34]  Seyed Ghassem Miremadi,et al.  A non-intrusive portable fault injection framework to assess reliability of FPGA-based designs , 2013, 2013 International Conference on Field-Programmable Technology (FPT).

[35]  J.N. Tombs,et al.  Selective Protection Analysis Using a SEU Emulator: Testing Protocol and Case Study Over the Leon2 Processor , 2007, IEEE Transactions on Nuclear Science.

[36]  Heather M. Quinn,et al.  A Test Methodology for Determining Space Readiness of Xilinx SRAM-Based FPGA Devices and Designs , 2009, IEEE Transactions on Instrumentation and Measurement.

[37]  Gabriel L. Nazar,et al.  Fast single-FPGA fault injection platform , 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[38]  J. Napoles,et al.  A Complete Emulation System for Single Event Effects Analysis , 2008, 2008 4th Southern Conference on Programmable Logic.

[39]  Antonio Torralba,et al.  Improving the design process of VLSI circuits by means of a hardware debugging system: UNSHADES-1 framework , 2002, IEEE 2002 28th Annual Conference of the Industrial Electronics Society. IECON 02.

[40]  Ana R. Cavalli,et al.  Use of invariant properties to evaluate the results of fault-injection-based robustness testing of protocol implementations , 2008, 2008 IEEE International Conference on Software Testing Verification and Validation Workshop.

[41]  Sergio D'Angelo,et al.  A fault injection tool for SRAM-based FPGAs , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

[42]  Javier Del Ser,et al.  Fast and accurate Single Bit Error injection into SRAM Based FPGAs , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

[43]  F. Chayab,et al.  Single Event Upset Characterization of the Virtex-4 Field Programmable Gate Array Using Proton Irradiation , 2006, 2006 IEEE Radiation Effects Data Workshop.

[44]  Seyed Ghassem Miremadi,et al.  A fast, flexible, and easy-to-develop FPGA-based fault injection technique , 2014, Microelectron. Reliab..

[45]  Felix Salfner,et al.  Software-Implemented Fault Injection at Firmware Level , 2010, 2010 Third International Conference on Dependability.

[46]  Simeon C. Ntafos,et al.  An Evaluation of Random Testing , 1984, IEEE Transactions on Software Engineering.

[47]  M. Wirthlin,et al.  SEU-induced persistent error propagation in FPGAs , 2005, IEEE Transactions on Nuclear Science.

[48]  Mario García-Valderas,et al.  Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection , 2012, IEEE Transactions on Computers.

[49]  J.N. Tombs,et al.  Fault Injection Analysis of Bidirectional Signals , 2009, IEEE Transactions on Nuclear Science.

[50]  R. Leveugle,et al.  Using run-time reconfiguration for fault injection applications , 2001, IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188).

[51]  Mario García-Valderas,et al.  SET Emulation Under a Quantized Delay Model , 2007, DFT.

[52]  M. Wirthlin,et al.  Fine-Grain SEU Mitigation for FPGAs Using Partial TMR , 2008, IEEE Transactions on Nuclear Science.

[53]  Luca Sterpone,et al.  A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing , 2013, IEEE Transactions on Computers.

[54]  Tommy Kuhn,et al.  Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection , 2013, 2013 International Conference on Field-Programmable Technology (FPT).

[55]  Alan D. George,et al.  Acceleration of FPGA Fault Injection Through Multi-Bit Testing , 2010, ERSA.

[56]  M. Caffrey,et al.  Domain Crossing Errors: Limitations on Single Device Triple-Modular Redundancy Circuits in Xilinx FPGAs , 2007, IEEE Transactions on Nuclear Science.

[57]  Mihalis Psarakis,et al.  A low-cost SEU fault emulation platform for SRAM-based FPGAs , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

[58]  W. H. Robinson,et al.  Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing , 2013, IEEE Transactions on Nuclear Science.

[59]  K.S. Morgan,et al.  SRAM FPGA Reliability Analysis for Harsh Radiation Environments , 2009, IEEE Transactions on Nuclear Science.

[60]  Gary Swift,et al.  VIRTEX-4 VQ static SEU Characterization Summary , 2008 .

[61]  L. Entrena,et al.  SET Emulation Considering Electrical Masking Effects , 2009, IEEE Transactions on Nuclear Science.

[62]  Ravishankar K. Iyer,et al.  SymPLFIED: Symbolic program-level fault injection and error detection framework , 2008, 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN).