Exact two-level minimization of hazard-free logic with multiple-input changes

This paper describes a new method for exact hazard-free logic minimization of Boolean functions. Given an incomuletelvspecijkd Boole~n@ction.Vthe method produces a mini&l su& of-products implementation which is hazard-free for a given set of multiple-input changes, if such a solution exists. The method is a constrained version of the Q&e-McCluskey algon’thm. It has been automated andapplied to a number of examples. Results are compared with results of a comparable non-hazard-free method (espresso-exact). Overhead due to hazard-elimination is shown to be negligible.

[1]  Paul T. Hulina,et al.  Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits , 1972, Inf. Control..

[2]  Robert K. Brayton,et al.  Synthesis of hazard-free asynchronous circuits from graphical specifications , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[3]  Ganesh Gopalakrishnan,et al.  SHILPA: a high-level synthesis system for self-timed circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[4]  Jochen Beister A Uniried Approach toCombinational Hazards , 1974 .

[5]  Edward J. McCluskey,et al.  Logic design principles - with emphasis on testable semicustom circuits , 1986, Prentice Hall series in computer engineering.

[6]  Polly Siegel,et al.  Asynchronous Communications Chip , 1994 .

[7]  David L. Dill,et al.  Automatic synthesis of locally-clocked asynchronous state machines , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[8]  Kenneth Y. Yun,et al.  Synthesis of 3D asynchronous state machines , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[9]  Alberto Sangiovanni-Vincentelli,et al.  Logic synthesis for vlsi design , 1989 .

[10]  Alain J. Martin Compiling communicating processes into delay-insensitive VLSI circuits , 2005, Distributed Computing.

[11]  Erik Brunvand,et al.  Translating concurrent programs into delay-insensitive circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[12]  Edward B. Eichelberger,et al.  Hazard Detection in Combinational and Sequential Switching Circuits , 1964, IBM J. Res. Dev..

[13]  Robert K. Brayton,et al.  Hazard prevention in combinational circuits , 1990, Twenty-Third Annual Hawaii International Conference on System Sciences.

[14]  Teresa H. Y. Meng,et al.  Synthesis of timed asynchronous circuits , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[15]  Stephen H. Unger,et al.  Asynchronous sequential switching circuits , 1969 .

[16]  Luciano Lavagno,et al.  Synthesis for testability techniques for asynchronous circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  David S. Kung Hazard-non-increasing gate-level optimization algorithms , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[18]  Edward J. McCluskey,et al.  Introduction to the theory of switching circuits , 1965 .

[19]  P. A. Subrahmanyam,et al.  A path-oriented approach for reducing hazards in asynchronous designs , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[20]  Steven M. Nowick,et al.  Automatic synthesis of burst-mode asynchronous controllers , 1993 .

[21]  Robert B. McGhee Some Aids to the Detection of Hazards in Combinational Switching Circuits , 1969, IEEE Transactions on Computers.

[22]  Alberto L. Sangiovanni-Vincentelli,et al.  Multiple-Valued Minimization for PLA Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Giovanni De Micheli,et al.  Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs , 1993, 30th ACM/IEEE Design Automation Conference.

[24]  Jon G. Bredeson Synthesis of multiple input-change hazard-free combinational switching circuits without feedback† , 1975 .

[25]  Hugo De Man,et al.  Optimized synthesis of asynchronous control circuits from graph-theoretic specifications , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[26]  Steven M. Nowick,et al.  UCLOCK: automated design of high-performance unclocked state machines , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[27]  Teresa H. Y. Meng,et al.  Automatic synthesis of asynchronous circuits from high-level specifications , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Mark E. Dean,et al.  The design of a high-performance cache controller: a case study in asynchronous synthesis , 1993, Integr..

[29]  Steven M. Burns Automated Compilation of Concurrent Programs into Self-Timed Circuits , 1988 .

[30]  Luciano Lavagno,et al.  Algorithms for synthesis of hazard-free asynchronous circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[31]  Jerzy Frackowiak Methoden der Analyse und Synthese von hasardarmen Schaltnetzen mit minimalen Kosten II , 1974, J. Inf. Process. Cybern..

[32]  Kenneth Y. Yun,et al.  Practical asynchronous controller design , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[33]  Peter A. Beerel,et al.  Automatic gate-level synthesis of speed-independent circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[34]  H.-J. Mathony Universal logic design algorithm and its application to the synthesis of two-level switching circuits , 1989 .

[35]  Tam-Anh Chu,et al.  Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .

[36]  David L. Dill,et al.  Synthesis of asynchronous state machines using a local clock , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.