Hardware accelerated smart-card software evaluation supported by information leakage and activity sensors

System integration density increased tremendously in recent years, resulting in various problems for designers. First, a variety of dependability issues were a direct consequence from high clock frequencies and system-on-chip complexity, such as thermal, power, and stability challenges. Furthermore, deep sub-micron semiconductor processes were increasingly prone to single-event-upsets and multiple-event-upsets caused by logic degradation and environmental sources. Besides these reliability issues, the intentional introduction of faults into the system by adversaries, is of increasing concern to system developers of smart-cards. Therefore, there is a strong need for hardware-accelerated evaluation techniques during the design phase to identify weaknesses in cryptographic software implementations. To map power and fault models to such FPGA-based evaluation systems, characterization and benchmark approaches are described in literature, using general purpose benchmark software. Unfortunately, such non-specialized software can lead to various evaluation problems. Therefore, this paper proposes an hardware-accelerated methodology for the investigation of software implementations in the security and dependability domains. The applicability of the approach has been shown using a general available system-on-chip implementation.