论文信息 - An I/O Line Configuration and Organization of DRAM

An I/O Line Configuration and Organization of DRAM

For state-of-the-art DRAM, the core operating speed is around 200 Mb/s. However, data is transferred by 7 Gb/s/pin for GDDR5 (R. Rho et al., IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 120–133, 2010; T.-Y. Oh et al., IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 120–133, 2011; D. Shin et al., IEEE Symp. on Very Large Scale Integr. Circuits Dig. Tech. Papers, pp. 138–139, 2009). This is possible because pre-fetch scheme is employed. In this session, we explain the pre-fetch scheme and global IO configuration for understanding speed limits restricted by DRAM core operation.

Chulwoo Kim | Junyoung Song | Hyun-Woo Lee

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