Adaptive WTA With an Analog VLSI Neuromorphic Learning Chip

In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system

[1]  Shih-Chii Liu,et al.  A winner-take-all spiking network with spiking inputs , 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

[2]  Paul E. Hasler,et al.  A high-resolution non-volatile analog memory cell , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[3]  H. Markram,et al.  Regulation of Synaptic Efficacy by Coincidence of Postsynaptic APs and EPSPs , 1997, Science.

[4]  Alan F. Murray,et al.  Citcuits for VLSI Implementation of Temporally Asymmetric Hebbian Learning , 2001, NIPS.

[5]  Alan F. Murray,et al.  Synchrony Detection by Analogue VLSI Neurons with Bimodal STDP Synapses , 2003, NIPS.

[6]  Davide Badoni,et al.  Spike-Driven Synaptic Plasticity: Theory, Simulation, VLSI Implementation , 2000, Neural Computation.

[7]  Wulfram Gerstner,et al.  Spike-Based Compared to Rate-Based Hebbian Learning , 1998, NIPS.

[8]  A. Hodgkin,et al.  Currents carried by sodium and potassium ions through the membrane of the giant axon of Loligo , 1952, The Journal of physiology.

[9]  S. Nagata,et al.  An electronic model of the retina , 1970 .

[10]  Mehdi Azadmehr,et al.  A foveated AER imager chip [address event representation] , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[11]  Rahul Sarpeshkar,et al.  A Low-Power Wide-Dynamic-Range Analog VLSI Cochlea , 1998 .

[12]  M A Arbib,et al.  Competitive Hebbian learning and the hippocampal place cell system: Modeling the interaction of visual and path integration cues , 2001, Hippocampus.

[13]  Alan F. Murray,et al.  Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI , 2005, IEEE Transactions on Neural Networks.

[14]  S. Tam,et al.  An electrically trainable artificial neural network (ETANN) with 10240 'floating gate' synapses , 1990, International 1989 Joint Conference on Neural Networks.

[15]  Alejandro Linares-Barranco,et al.  Test Infrastructure for Address-Event-Representation Communications , 2005, IWANN.

[16]  Eugene M. Izhikevich,et al.  Relating STDP to BCM , 2003, Neural Computation.

[17]  Andreas G. Andreou,et al.  A Contrast Sensitive Silicon Retina with Reciprocal Synapses , 1991, NIPS.

[18]  Bernabé Linares-Barranco,et al.  An arbitrary kernel convolution AER-transceiver chip for real-time image filtering , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[19]  Carver Mead,et al.  Analog VLSI and neural systems , 1989 .

[20]  Philipp Häfliger,et al.  An Asynchronous 4-to-4 AER Mapper , 2005, IWANN.

[21]  Philipp Häfliger,et al.  A multi-level static memory cell , 2003, ISCAS.

[22]  Giacomo Indiveri,et al.  A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity , 2006, IEEE Transactions on Neural Networks.

[23]  Eric A. Vittoz,et al.  A communication architecture tailored for analog VLSI artificial neural networks: intrinsic performance and limitations , 1994, IEEE Trans. Neural Networks.

[24]  T. Bliss,et al.  Long‐lasting potentiation of synaptic transmission in the dentate area of the anaesthetized rabbit following stimulation of the perforant path , 1973, The Journal of physiology.

[25]  Wulfram Gerstner,et al.  A neuronal learning rule for sub-millisecond temporal coding , 1996, Nature.

[26]  Shih-Chii Liu,et al.  Feature competition in a spike-based winner-take-all VLSI network , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[27]  Ph. Hafliger Asynchronous event redirecting in bio-inspired communication , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[28]  N. Spruston,et al.  Action potential initiation and backpropagation in neurons of the mammalian CNS , 1997, Trends in Neurosciences.

[29]  L. Abbott,et al.  Competitive Hebbian learning through spike-timing-dependent synaptic plasticity , 2000, Nature Neuroscience.

[30]  W. Denk,et al.  Dendritic spines as basic functional units of neuronal integration , 1995, Nature.

[31]  Shih-Chii Liu,et al.  AER EAR: A Matched Silicon Cochlea Pair With Address Event Representation Interface , 2007, IEEE Trans. Circuits Syst. I Regul. Pap..

[32]  Mehdi Azadmehr A foveated aer imager chip , 2005 .

[33]  R. Kempter,et al.  Hebbian learning and spiking neurons , 1999 .

[34]  Misha Mahowald,et al.  A silicon model of early visual processing , 1993, Neural Networks.

[35]  André van Schaik,et al.  AER EAR: A Matched Silicon Cochlea Pair With Address Event Representation Interface , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[36]  Philipp Hafliger A spike based learning rule and its implementation in analog hardware , 2000 .

[37]  Tobi Delbrück,et al.  A 128 X 128 120db 30mw asynchronous vision sensor that responds to relative intensity change , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[38]  Carver A. Mead,et al.  Neuromorphic electronic systems , 1990, Proc. IEEE.

[39]  Philipp Häfliger,et al.  A time domain winner-take-all network of integrate-and-fire neurons , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[40]  John Lazzaro,et al.  Circuit Models of Sensory Transduction in the Cochlea , 1989, Analog VLSI Implementation of Neural Systems.

[41]  Florentin Wörgötter,et al.  A neuromorphic depth-from-motion vision model with STDP adaptation , 2006, IEEE Transactions on Neural Networks.

[42]  D. O. Hebb,et al.  The organization of behavior , 1988 .

[43]  Misha Mahowald,et al.  A Spike Based Learning Neuron in Analog VLSI , 1996, NIPS.

[44]  Misha A. Mahowald,et al.  An Analog VLSI System for Stereoscopic Vision , 1994 .

[45]  E. Culurciello,et al.  A biomorphic digital image sensor , 2003, IEEE J. Solid State Circuits.