A Novel 14-Transistors Low-Power High-Speed PPM Adder

In this paper we mainly deal with design and simulation of different redundant-binary full adder (Plus-Plus-Minus Adder) topologies using minimum number of transistors. These PPM adder topologies are simulated to evaluate their performance in total power dissipation, speed, and PDP. Compared with other PPM adder designs, the proposed novel design full adder topology features higher computing speed and lower energy (power delay product) operation. The simulation results reveal that the overall PDP for the proposed circuits have been improved by 10 % to 15 % at the supply voltage of 1.8V when compared with the reported PPM adder topologies at 0.18µm CMOS technology.

[1]  Ghassem Jaberipur,et al.  A Nonspeculative Maximally Redundant Signed Digit Adder , 2008 .

[2]  山品 正勝,et al.  Cmos logic circuit , 1997 .

[3]  Zine-Eddine Abid,et al.  New designs of Redundant-Binary full Adders and its applications , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[4]  Magdy A. Bayoumi,et al.  Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Mohamed A. Elgamel,et al.  Design methodologies for high-performance noise-tolerant XOR-XNOR circuits , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[7]  Mohamed A. Elgamel,et al.  Noise tolerant low voltage XOR-XNOR for fast arithmetic , 2003, GLSVLSI '03.

[8]  Tarek Darwish,et al.  Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[9]  John P. Uyemura,et al.  CMOS Logic Circuit Design , 1992 .

[10]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[11]  Jean-Michel Muller,et al.  JANUS, an on-line multiplier/divider for manipulating large numbers , 1989, Proceedings of 9th Symposium on Computer Arithmetic.

[12]  Wei Wang,et al.  New designs of 14-transistor PPM adder , 2005, Canadian Conference on Electrical and Computer Engineering, 2005..

[13]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .