Aging Mitigation in FPGAs Considering Delay, Power, and Temperature

Field programmable gate array (FPGA) devices are highly susceptible to transistor aging, mainly through the bias temperature instability (BTI) phenomenon. BTI can be modeled as threshold voltage increase in MOSFET transistors, which leads to the degradation in device performance. As technology scales, leakage power has turned into a major portion of FPGA total power consumption. In this paper, we study the mutual effects of BTI and leakage power by considering the temperature changes in the basic components of FPGAs. Our analysis shows that while the leakage-power reduction caused by BTI may be considered desirable, a bit-flipping scheme should still be employed to mitigate device degradation. We present an optimization problem to optimize the device performance over the device's lifetime. A postrouting aging-aware timing analysis method is also proposed to find the best flipping frequency. The simulation results show that bit flipping at a proper frequency may reduce the power consumption of device by about 5% while keeping the critical path delay below a given constraint.

[1]  Bashir M. Al-Hashimi,et al.  Aging Benefits in Nanometer CMOS Designs , 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Vaughn Betz,et al.  Should FPGAS abandon the pass-gate? , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[3]  Anurag Tiwari,et al.  Enhanced reliability of finite-state machines in FPGA through efficient fault detection and correction , 2005, IEEE Transactions on Reliability.

[4]  Yu Cao,et al.  Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology , 2007, IEEE Transactions on Device and Materials Reliability.

[5]  Houman Homayoun,et al.  Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[6]  Hans Jurgen Mattausch,et al.  Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions , 2014, IEEE Transactions on Device and Materials Reliability.

[7]  Abdulazim Amouri,et al.  Investigation of aging effects in different implementations and structures of programmable routing resources of FPGAs , 2012, 2012 International Conference on Field-Programmable Technology.

[8]  Paolo Prinetto,et al.  SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs , 2015, TRETS.

[9]  Miodrag Potkonjak,et al.  Enhanced FPGA reliability through efficient run-time fault reconfiguration , 2000, IEEE Trans. Reliab..

[10]  Abdulazim Amouri,et al.  Altering LUT configuration for wear-out mitigation of FPGA-mapped designs , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[11]  Bashir M. Al-Hashimi,et al.  Reliable Power Gating With NBTI Aging Benefits , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Swarup Bhunia,et al.  Low-Power Variation-Tolerant Design in Nanometer Silicon , 2011 .

[13]  Noen Given,et al.  A Novel Gate-level NBTI Delay Degradation Model with Stacking Effect , 2007 .

[14]  Narayanan Vijaykrishnan,et al.  Toward Increasing FPGA Lifetime , 2008, IEEE Transactions on Dependable and Secure Computing.

[15]  Jörg Henkel,et al.  Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures , 2013, 2013 IEEE International Test Conference (ITC).

[16]  Juanjo Noguera,et al.  Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration , 2011, 2011 Design, Automation & Test in Europe.

[17]  Abdulazim Amouri,et al.  Investigation of NBTI and PBTI induced aging in different LUT implementations , 2011, 2011 International Conference on Field-Programmable Technology.

[18]  Jan M. Rabaey,et al.  Ultralow-Power Design in Near-Threshold Region , 2010, Proceedings of the IEEE.

[19]  Yu Wang,et al.  Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Tim Tuan,et al.  Active leakage power optimization for FPGAs , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Steven Trimberger,et al.  A 90-nm Low-Power FPGA for Battery-Powered Applications , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Ulf Schlichtmann,et al.  A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits , 2014, Microelectron. Reliab..

[23]  Bogdan Tudor,et al.  MOSRA: An efficient and versatile MOS aging modeling and reliability analysis solution for 45nm and below , 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

[24]  Russell Tessier,et al.  Tolerating operational faults in cluster-based FPGAs , 2000, FPGA '00.

[25]  James H. Stathis,et al.  Reliability of advanced high-k/metal-gate n-FET devices , 2010, Microelectron. Reliab..

[26]  Yanling Wang,et al.  Prediction of NBTI Degradation in Dynamic Voltage Frequency Scaling Operations , 2016, IEEE Transactions on Device and Materials Reliability.

[27]  Mircea R. Stan,et al.  Modeling and experimental demonstration of accelerated self-healing techniques , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[28]  Andrew R. Brown,et al.  Impact of NBTI/PBTI on SRAM Stability Degradation , 2011, IEEE Electron Device Letters.

[29]  Yu Cao,et al.  Compact Modeling of Statistical BTI Under Trapping/Detrapping , 2013, IEEE Transactions on Electron Devices.

[30]  Jonathan Rose,et al.  Quantifying and Exploring the Gap Between FPGAs and ASICs , 2009 .

[31]  Wayne Luk,et al.  An Overview of Low-Power Techniques for Field-Programmable Gate Arrays , 2008, 2008 NASA/ESA Conference on Adaptive Hardware and Systems.

[32]  Hao Luo,et al.  Aging-Leakage Tradeoffs Using Multi-Vth Cell Library , 2016, 2016 IEEE 25th Asian Test Symposium (ATS).