High Speed , High Bandwidth External Cache Bus with A Center-Tapped-Termination Scheme

Abstract -This paper describes the implementation of an external L3 Cache memory bus used in ItaniumTM processor. The cache bus has been designed for adequate bandwidth required in high-end servers, and provides data to the processor at the processor core frequency. High-speed I/O circuits used to accomplish this state-of-the-art bus design are discussed in detail. The center-tapped-termination (CTT) scheme used to achieve high bus speeds is also discussed. The packaging technology and the high-speed package design techniques used to meet our performance targets are also presented. The design has been thoroughly validated and has successfully met our performance requirements.