Inter-task WCET computation for a-way instruction caches

In hard real-time applications, Worst Case Execution Time (WCET) is used to check time constraints of the whole system but is only computed at the task level. As most WCET computation methods assume a conservative approach to handle the processor state before the execution of a task, the inter-task analysis of long effect hardware features should improve the accuracy of the result. As an example, we propose to analyze the behavior of an A-way associative instruction cache, by combining inter-and intra-task instruction cache analysis. The aim is to estimate more accurately the number of cache misses due to task chaining by considering task Entry and Exit states along the inter-task analysis. The initial tasks WCETs can be computed by any existing single-task approach that models the instruction cache behavior. A second method is also introduced in this paper which consists in injecting the inter-task cache states in the intra-task WCET analysis, to get more precise numbers.

[1]  Pascal Sainrat,et al.  Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis , 2007, 2007 International Symposium on Industrial Embedded Systems.

[2]  Sharad Malik,et al.  Efficient microarchitecture modeling and path analysis for real-time software , 1995, Proceedings 16th IEEE Real-Time Systems Symposium.

[3]  Raimund Kirner,et al.  Automatic timing model generation by CFG partitioning and model checking , 2005, Design, Automation and Test in Europe.

[4]  Yudong Tan,et al.  Integrated Intra- and Inter-task Cache Analysis for Preemptive Multi-tasking Real-Time Systems , 2004, SCOPES.

[5]  Reinhard Wilhelm,et al.  Applying Compiler Techniques to Cache Behavior Prediction , 2007 .

[6]  Yudong Tan,et al.  Timing analysis for preemptive multi-tasking real-time systems with caches , 2004 .

[7]  Isabelle Puaut,et al.  Low-complexity algorithms for static cache locking in multitasking hard real-time systems , 2002, 23rd IEEE Real-Time Systems Symposium, 2002. RTSS 2002..

[8]  Sharad Malik,et al.  Cache modeling for real-time software: beyond direct mapped instruction caches , 1996, 17th IEEE Real-Time Systems Symposium.

[9]  Peter H. Feiler,et al.  Embedded System Architecture Analysis Using SAE AADL , 2004 .

[10]  Frank Müller,et al.  Timing Analysis for Instruction Caches , 2000, Real-Time Systems.

[11]  Rolf Ernst,et al.  Cache Effects in Multi Process Real-Time Systems with Preemptive Scheduling , .

[12]  Pascal Sainrat,et al.  PapaBench: a Free Real-Time Benchmark , 2006, WCET.

[13]  Pascal Sainrat,et al.  OTAWA, a Framework for Experimenting WCET Computations , 2006 .

[14]  Abdur Rakib,et al.  Component-Wise Instruction-Cache Behavior Prediction , 2004, ATVA.

[15]  Yudong Tan,et al.  Timing analysis for preemptive multi-tasking real-time systems with caches , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.