NAND flash memory has been widely adopted as a storage medium in consumer electronics and portable devices due to its shock resistance, high density, low cost, low power consumption, non-volatility, and low access latency natures. It could be classified into Single-Level Cell (SLC) and Multi-Level Cell (MLC). SLC is the earlier design of flash memory and could store one bit per cell. Numerous excellent management schemes have been proposed for SLC. In recent years, MLC, which stores two or more bits per cell, has gradually replaced SLC due to its lower cost and higher density. However, MLC also brings new constraints, i.e., no partial programming and sequential page writes within a block, to the management. This paper proposes a novel mapping scheme for MLC. The goals of our research are to avoid time out by decreasing dummy page writes, to get a better response time by decreasing live page copying, and to prolong the life span of flash memory by decreasing block erasures.
[1]
Li-Pin Chang,et al.
Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs
,
2008,
2008 Asia and South Pacific Design Automation Conference.
[2]
Tei-Wei Kuo,et al.
Efficient identification of hot data for flash memory storage systems
,
2006,
TOS.
[3]
Young-Jin Kim,et al.
LAST: locality-aware sector translation for NAND flash memory-based storage systems
,
2008,
OPSR.
[4]
Tei-Wei Kuo,et al.
An adaptive striping architecture for flash memory storage systems of embedded systems
,
2002,
Proceedings. Eighth IEEE Real-Time and Embedded Technology and Applications Symposium.
[5]
Sang-Won Lee,et al.
A log buffer-based flash translation layer using fully-associative sector translation
,
2007,
TECS.