Balancing power signature in secure systems

Dual-rail code, return-to-spacer protocol and hazard-free logic is used to make power consumption of synchronous circuits independent from data processed. A new compact dual-rail flip-flop is designed, whose power consumption is also data-independent. A method for negative gate optimisation of dual-rail logic is described, which results in faster and smaller circuits. A tool for dual-rail circuit optimisation is developed. The tool is interfaced to the Cadence CAD system. Dual-rail and single-rail benchmarks are simulated and compared.

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