Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory

By storing multibit per cell, multilevel cell (MLC) NAND flash memory achieves high storage capacity, but sacrificing data reliability. Error correction codes, such as Bose–Chaudhuri–Hocquenghem (BCH) codes, are widely used to ensure data reliability. However, high raw bit error rates induced by interference noises make BCH codes become insufficient to guarantee data reliability. Low-density parity-check (LDPC) codes are considered as the replacement due to the stronger error correction capability. Nevertheless, directly exploiting LDPC codes introduces a concern about decoding latency because of their iterative decoding in the soft decision process. To develop effective LDPC decoding algorithms, it is necessary to have a more profound understanding on flash failure patterns. This paper first observes the pair-bit errors (PBEs) characteristic of MLC NAND flash memory on a real field-programmable gate array testing platform, then proposes a PBE-aware LDPC (PAL) decoding scheme-based upon this observation, in which PBE provides the promotion information for LDPC decoding to reduce decoding latency. Simulation results show that the decoding latency can be reduced by up to 54%, compared with the conventional LDPC codes.

[1]  Wonyong Sung,et al.  Least squares based cell-to-cell interference cancelation technique for multi-level cell nand flash memory , 2012, 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

[2]  Maha Elsabrouty,et al.  Simplified variable-scaled min sum LDPC decoder for irregular LDPC codes , 2014, 2014 IEEE 11th Consumer Communications and Networking Conference (CCNC).

[3]  Nanning Zheng,et al.  Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory , 2014, 2014 30th Symposium on Mass Storage Systems and Technologies (MSST).

[4]  You Zhou,et al.  Characterizing 3D Floating Gate NAND Flash , 2017, SIGMETRICS.

[5]  Arif Merchant,et al.  Flash Reliability in Production: The Expected and the Unexpected , 2016, FAST.

[6]  Liyan Qiao,et al.  A Joint Decoding Strategy of Non-binary LDPC Codes Based on Retention Error Characteristics for MLC NAND Flash Memories , 2016, 2016 Sixth International Conference on Instrumentation & Measurement, Computer, Communication and Control (IMCCC).

[7]  Cong Xu,et al.  Memory and Storage System Design with Nonvolatile Memory Technologies , 2015, IPSJ Trans. Syst. LSI Des. Methodol..

[8]  Nanning Zheng,et al.  LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives , 2013, FAST.

[9]  Osman S. Unsal,et al.  Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[10]  Richard D. Wesel,et al.  Soft Information for LDPC Decoding in Flash: Mutual-Information Optimized Quantization , 2011, 2011 IEEE Global Telecommunications Conference - GLOBECOM 2011.

[11]  Qiao Li,et al.  Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory , 2016, FAST.

[12]  Jongmoo Choi,et al.  Hybrid solid state drives for improved performance and enhanced lifetime , 2013, 2013 IEEE 29th Symposium on Mass Storage Systems and Technologies (MSST).

[13]  Dong Wook Lee,et al.  The Operation Algorithm for Improving the Reliability of TLC (Triple Level Cell) NAND Flash Characteristics , 2011, 2011 3rd IEEE International Memory Workshop (IMW).

[14]  Shuhei Tanakamaru,et al.  Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme , 2012, 2012 IEEE International Solid-State Circuits Conference.

[15]  Onur Mutlu,et al.  Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[16]  Paul H. Siegel,et al.  Error characterization and coding schemes for flash memories , 2010, 2010 IEEE Globecom Workshops.

[17]  Qiao Li,et al.  Improving LDPC performance via asymmetric sensing level placement on flash memory , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[18]  Harry Q. Pon,et al.  Reliability issues studied in Solid-State Drives , 2014, 2014 IEEE 6th International Memory Workshop (IMW).

[19]  Ren-Shuo Liu,et al.  EC-Cache: Exploiting error locality to optimize LDPC in NAND flash-based SSDs , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[20]  Yiran Chen,et al.  FlexLevel: A novel NAND flash storage system design for LDPC latency reduction , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[21]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[22]  Steven Swanson,et al.  Understanding the impact of power loss on flash memory , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[23]  Fei Wu,et al.  FPGA-based failure mode testing and analysis for MLC NAND flash memory , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[24]  Tong Zhang,et al.  Techniques for embracing intra-cell unbalanced bit error characteristics in MLC NAND flash memory , 2010, 2010 IEEE Globecom Workshops.

[25]  Paul H. Siegel,et al.  Characterizing flash memory: Anomalies, observations, and applications , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[26]  Qiang Wu,et al.  A Large-Scale Study of Flash Memory Failures in the Field , 2015, SIGMETRICS 2015.

[27]  Fei Wu,et al.  CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND Flash , 2017, 2017 IEEE International Conference on Computer Design (ICCD).

[28]  Onur Mutlu,et al.  Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery , 2015, 2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks.

[29]  Onur Mutlu,et al.  Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation , 2013, ICCD.

[30]  Wonyong Sung,et al.  Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[31]  Hai Jin,et al.  LaLDPC: Latency-aware LDPC for Read Performance Improvement of Solid State Drives , 2017 .

[32]  Nanning Zheng,et al.  Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[33]  Yong Liang Guan,et al.  Retention-Aware Belief-Propagation Decoding for NAND Flash Memory , 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

[34]  Wonyong Sung,et al.  A high-speed layered min-sum LDPC decoder for error correction of NAND Flash memories , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

[35]  Xiaodong Zhang,et al.  Understanding intrinsic characteristics and system implications of flash memory based solid state drives , 2009, SIGMETRICS '09.

[36]  Young-Pil Kim,et al.  Reducing MLC flash memory retention errors through Programming Initial Step Only , 2015, 2015 31st Symposium on Mass Storage Systems and Technologies (MSST).

[37]  Tong Zhang,et al.  Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications , 2012, IEEE International Symposium on High-Performance Comp Architecture.

[38]  Chih-Tsun Huang,et al.  Reliability analysis and improvement for multi-level non-volatile memories with soft information , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[39]  Paul H. Siegel,et al.  Characterization and error-correcting codes for TLC flash memories , 2012, 2012 International Conference on Computing, Networking and Communications (ICNC).

[40]  Fei Wu,et al.  A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding Performance , 2017, ACM Trans. Embed. Comput. Syst..

[41]  Onur Mutlu,et al.  Threshold voltage distribution in MLC NAND flash memory: Characterization, analysis, and modeling , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[42]  Piero Olivo,et al.  LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives , 2019, IEEE Transactions on Emerging Topics in Computing.