Transistor chaining and transistor reordering in the design of CMOS complex gates

The problem of chaining transistors in the layout of CMOS complex gates is addressed. The layouts are partitioned into two classes; namely, dual independent and dual dependent. A dual independent layout is a layout for which the optimality of the solution is independent of the duality between the PMOS and NMOS networks of a CMOS complex gate (e.g., dynamic CMOS). A dual dependent layout is a layout for which the optimality of the solution is dependent on the dual property of a CMOS complex gate (e.g., static CMOS). Optimization algorithms for the two classes of layouts differ, and one algorithm for each is presented in this dissertation. The dual dependent layout problem for non-series/parallel circuits is NP-hard; therefore, an efficient heuristic is proposed for its solution. The heuristic algorithm has linear time complexity in terms of the number of transistors in the circuit, and produces optimal solutions in 92 percent of the test cases. The algorithm presented for dual independent layout generation utilizes a new tree representation for non-series/parallel circuits to perform transistor reordering. It is a two stage algorithm which determines an optimal reordering of transistors in the circuit, and a layout of optimum width. An algorithm which determines the tree representation of an arbitrary circuit is presented. The algorithm accepts a SPICE description of a complex gate as input, and produces a tree representation of the circuit. Reordering transistors in a CMOS complex gate can result in the reduction of layout area, and a technique for doing this in dual independent layouts is presented. Since reordering the transistors in a gate may have a significant effect on the timing behavior of the circuit, a simulation-based investigation of this effect is performed. It is shown that for many practical circuits the transistor order does not have a significant effect on the propagation delay; therefore, transistor reordering to decrease layout area in most cases does not have an adverse effect on the design of the circuit.