Interfacing Cores and Routers in Network-on-Chip Using GALS
暂无分享,去创建一个
[1] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[2] C. P. Ravikumar,et al. VLSI implementation of a wormhole router using virtual channels , 1994, Proceedings of TENCON'94 - 1994 IEEE Region 10's 9th Annual International Conference on: 'Frontiers of Computer Technology'.
[3] Kenneth Y. Yun,et al. Pausible clocking: a first step toward heterogeneous systems , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.
[4] Alf Johansson,et al. On Connecting Cores to Packet Switched On-Chip Networks: A Case Study with MicroBlaze Processor Cores , 2004 .
[5] Steven M. Nowick,et al. A low-latency FIFO for mixed-clock systems , 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.
[6] Axel Jantsch,et al. A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.
[7] Ahmed Amine Jerraya,et al. Network interface generation for MPSOC: from communication service requirements to RTL implementation , 2004, Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004..
[8] J.N. Seizovic,et al. Pipeline synchronization , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.
[9] Axel Jantsch,et al. Networks on chip , 2003 .