A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications
暂无分享,去创建一个
[1] Mahmut T. Kandemir,et al. Improving Cache Locality by a Combination of Loop and Data Transformation , 1999, IEEE Trans. Computers.
[2] David R. Kaeli,et al. Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance , 1999, IEEE Trans. Computers.
[3] Eric Rotenberg,et al. A Trace Cache Microarchitecture and Evaluation , 1999, IEEE Trans. Computers.
[4] M. Milenkovic,et al. A performance evaluation of memory hierarchy in embedded systems , 2003, Proceedings of the 35th Southeastern Symposium on System Theory, 2003..
[5] Scott McFarling,et al. Procedure merging with instruction caches , 1991, PLDI '91.
[6] Alan Jay Smith,et al. Evaluating Associativity in CPU Caches , 1989, IEEE Trans. Computers.
[7] Hiroshi Nakamura,et al. Augmenting Loop Tiling with Data Alignment for Improved Cache Performance , 1999, IEEE Trans. Computers.
[8] Norman P. Jouppi,et al. Improving direct-mapped cache performance by the addition of a small fully-associative cache and pre , 1990, ISCA 1990.
[9] Antonio Gonzalez,et al. A data cache with multiple caching strategies tuned to different types of locality , 1995, International Conference on Supercomputing.
[10] Josep Torrellas,et al. Optimizing the Instruction Cache Performance of the Operating System , 1998, IEEE Trans. Computers.
[11] Jack W. Davidson,et al. Profile guided code positioning , 1990, SIGP.
[12] Cosimo Antonio Prete,et al. A cache-aware program transformation technique suitable for embedded systems , 2002, Inf. Softw. Technol..
[13] V. Milutinovic,et al. Enhancing and Exploiting the Locality , 1999, IEEE Trans. Computers.
[14] Antonio González,et al. Randomized Cache Placement for Eliminating Conflicts , 1999, IEEE Trans. Computers.
[15] Pierre G. Paulin,et al. System-on-chip beyond the nanometer wall , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[16] Mateo Valero,et al. Eliminating cache conflict misses through XOR-based placement functions , 1997, ICS '97.
[17] Brad Calder,et al. Procedure placement using temporal ordering information , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.
[18] Cosimo Antonio Prete,et al. The ChARM tool for tuning embedded systems , 1997, IEEE Micro.
[19] Antonio González,et al. A locality sensitive multi-module cache with explicit management , 1999, ICS '99.