Reliability and performance-aware 3D SRAM design

In 3D integrated circuits, through-silicon-vias (TSVs) are used to connect different dies stacked on top of each other. These TSVs occupy significant silicon area and are many times larger than gates. Depending on the fabrication technique, TSVs can have different area and fabrication cost. TSVs can also cause reliability challenges for 3D ICs by reducing the yield of the chip. In this paper, we discuss how to perform physical design of bank-level 3D SRAM. We show that a tradeoff exists in terms of reliability and performance for 3D SRAMs. We also show the impact of via-first vs via-last TSVs on the layout quality of 3D SRAM designs. All our results are based on GDSII based layouts. Based on our results different SRAM organizations maybe chosen based on reliability versus performance tradeoff.

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