Counter Advance for Reliable Encryption in Phase Change Memory

The use of hardware encryption and new memory technologies such as phase change memory (PCM) are gaining popularity in a variety of server applications such as cloud systems. While PCM provides energy and density advantages over conventional DRAM memory, it faces endurance challenges. Such challenges are exacerbated when employing memory encryption as the stored data is essentially randomized, losing data locality and reducing or eliminating the effectiveness of energy and endurance aware encoding techniques. This results in increasing dynamic energy consumption and accelerated wear out. In this paper we propose <italic>counter advance</italic>, a technique to leverage the process of encryption to improve reliability and lifetime while maintaining low-energy and low-latency operation. Counter advance is compatible with standard error-correction codes (ECC) and error correction pointers (ECP), the standard for mitigating endurance faults in PCM. Counter advance achieves the same fault tolerance using three ECP pointers for a <inline-formula><tex-math notation="LaTeX">$10^{-4}$</tex-math><alternatives> <inline-graphic xlink:href="kline-ieq1-2861012.gif"/></alternatives></inline-formula> cell failure rate compared to the leading approach to consider energy savings and reliability for encrypted PCM (SECRET) using five ECP pointers. At a failure rate of <inline-formula><tex-math notation="LaTeX">$10^{-2}$</tex-math><alternatives> <inline-graphic xlink:href="kline-ieq2-2861012.gif"/></alternatives></inline-formula>, counter advance can achieve an uncorrectable bit error rate (UBER) of 10<inline-formula><tex-math notation="LaTeX">$^{-10}$</tex-math><alternatives> <inline-graphic xlink:href="kline-ieq3-2861012.gif"/></alternatives></inline-formula>, compared to <inline-formula> <tex-math notation="LaTeX">${<}10^{-4}$</tex-math><alternatives> <inline-graphic xlink:href="kline-ieq4-2861012.gif"/></alternatives></inline-formula> for SECRET, using six ECP pointers. This leads to a lifetime improvement of 3.8× while maintaining comparable energy consumption and access latency.

[1]  K. Gopalakrishnan,et al.  Phase change memory technology , 2010, 1001.1164.

[2]  Hsien-Hsin S. Lee,et al.  SAFER: Stuck-At-Fault Error Recovery for Memories , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[3]  Kartik Mohanram,et al.  SECRET: Smartly EnCRypted Energy efficienT non-volatile memories , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[4]  Morris J. Dworkin SP 800-38E. Recommendation for Block Cipher Modes of Operation: the XTS-AES Mode for Confidentiality on Storage Devices , 2010 .

[5]  Huiyang Zhou,et al.  Improving privacy and lifetime of PCM-based main memory , 2010, 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN).

[6]  Karin Strauss,et al.  Use ECP, not ECC, for hard failures in resistive memories , 2010, ISCA.

[7]  Phillip Rogaway,et al.  Efficient Instantiations of Tweakable Blockciphers and Refinements to Modes OCB and PMAC , 2004, ASIACRYPT.

[8]  Jun Yang,et al.  A durable and energy efficient main memory using phase change memory technology , 2009, ISCA '09.

[9]  B. Rogers,et al.  Improving Cost, Performance, and Security of Memory Encryption and Authentication , 2006, ISCA 2006.

[10]  H.-S. Philip Wong,et al.  Phase Change Memory , 2010, Proceedings of the IEEE.

[11]  John L. Henning SPEC CPU2006 benchmark descriptions , 2006, CARN.

[12]  Dan Feng,et al.  A wear-leveling-aware counter mode for data encryption in non-volatile memories , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[13]  Sivan Toledo,et al.  Phase-change memory: An architectural perspective , 2013, CSUR.

[14]  M.E. Hellman,et al.  Privacy and authentication: An introduction to cryptography , 1979, Proceedings of the IEEE.

[15]  Yiran Chen,et al.  Emerging non-volatile memories: Opportunities and challenges , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[16]  Zaid Al-Ars DRAM fault analysis and test generation , 2005 .

[17]  Hyunjin Lee,et al.  Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).