The Effect of Fault Secureness in Low Power Multiplier Designs

In this paper, the fault-secure multiplier designs of three characteristic multiplier designs are examined and compared in terms of integration area, power dissipation and performance. Real-time detection of any single fault is ensured for all the presented circuits, while the characteristics of each multiplier are illustrated. The experimental results taken, indicate that these characteristics change when the safety mechanisms are applied. Special attention is given to the fault-secure implementation of low power multipliers.