Fault simulation of I/sub DDQ/ tests for bridging faults in sequential circuits

The notion of indistinguishable pairs is introduced. Two methods to compute such pairs-an explicit scheme and an implicit scheme-are presented. The resulting fault simulation algorithms, list-based scheme and tree-based scheme are compared using a variety of faultlists and test sets. The performance of the tree-based scheme is found to be superior to the list-based scheme. Applications where the list-based scheme perform better are discussed.<<ETX>>

[1]  Rosa Rodríguez-Montañés,et al.  Analysis of bridging defects in sequential CMOS circuits and their current testability , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[2]  Wojciech Maly,et al.  Built-in current testing-feasibility study , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[3]  John Paul Shen,et al.  Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells , 1984, ITC.

[4]  W. H. Debany,et al.  Coverage of Node Shorts Using Internal Access and Equivalence Classes , 1993, VLSI Design.

[5]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[6]  Wojciech Maly,et al.  Realistic Fault Modeling for VLSI Testing , 1987, 24th ACM/IEEE Design Automation Conference.

[7]  Melvin A. Breuer,et al.  Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[9]  Sreejit Chakravarty,et al.  Algorithms for current monitor based diagnosis of bridging and leakage faults , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[10]  F. Joel Ferguson,et al.  Carafe: an inductive fault analysis tool for CMOS VLSI circuits , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[11]  Sreejit Chakravarty,et al.  Fast algorithms for computing I/sub DDQ/ tests for combinational circuits , 1996, Proceedings of 9th International Conference on VLSI Design.

[12]  Wu-Tung Cheng,et al.  Gentest: an automatic test-generation system for sequential circuits , 1989, Computer.

[13]  Sreejit Chakravarty,et al.  Algorithms for IDDQ measurement based diagnosis of bridging faults , 1992, J. Electron. Test..

[14]  Sreejit Chakravarty,et al.  Simulation and generation of IDDQ tests for bridging faults in combinational circuits , 1993, VTS.

[15]  Sreejit Chakravarty,et al.  A study of I/sub DDQ/ subset selection algorithms for bridging faults , 1994, Proceedings., International Test Conference.