Characterization and modelling of Si-substrate noise induced by RF signal propagating in TSV of 3D-IC stack

TSVs in 3D integrated circuits are a source of noise that can affect nearby transistor performance. So an analytical physics-based model of the TSV-to-substrate coupling is proposed to perform time domain or noise simulations. Silicon measurements at low frequencies and radiofrequencies are reported. Simulations are done using a software performing device and electromagnetic co-simulations. The model and simulations are validated by measurements. Simulations to study the sensitivity of the TSV structure to the layout show changes in the TSV-to-substrate coupling behavior.

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