An artificial retina chip with current-mode focal plane image processing functions

This paper describes an artificial retina chip consisting of an array of Variable Sensitivity Photo-Detector cells (VSPDs) which accomplishes both nondestructive output and programmable positive or negative sensitivity. Despite its simple structure, this VSPD array realizes programmable focal plane image processing by employing between-pixel current mode calculations, together with a novel addressing method in which filtering is executed by varying the addressing pattern generated by a scanning unit. The n-MOS VSPD pixel which we have designed consists of a pn photodiode and an n-MOS differential amplifier; the VSPD circuit has been optimized by SPICE simulation. Using a 2-/spl mu/m n-MOS process gives a pixel size of 35 (H)/spl times/26 (V) /spl mu/m/sup 2/ with a photodiode fill factor of 25%. The artificial retina chip which has been fabricated incorporates 256/spl times/256 pixels, 16 parallel output ports, and a random access function. The photosensitivity is 0.8 /spl mu/A/lx for a 1-ms accumulation time. We demonstrate image capture in video mode and edge extraction mode, and light spot tracing using pattern matching in conjunction with the random access function.

[1]  Eric R. Fossum,et al.  Architectures For Focal Plane Image Processing , 1989 .

[2]  K. Miyata,et al.  A 250000-pixel image sensor with FET amplification at each pixel for high-speed television cameras , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[3]  John L. Wyatt,et al.  The MIT Vision Chip Project: analog VLSI systems for fast image acquisition and early vision processing , 1991, Proceedings. 1991 IEEE International Conference on Robotics and Automation.

[4]  J Ohta,et al.  Dynamic optical neurochip using variable-sensitivity photodiodes. , 1991, Optics letters.

[5]  Kazuo Kyuma,et al.  Artifical retina devices-fast front ends for neural image processing systems , 1993, Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan).

[6]  Francis Devos,et al.  A programmable artificial retina , 1993 .

[7]  Kazuo Kyuma,et al.  Optical neural chips , 1994, IEEE Micro.

[8]  Kazuo Kyuma,et al.  Artificial retinas — fast, versatile image processors , 1994, Nature.

[9]  O. Vellacott.  CMOS in camera , 1994 .

[10]  J. Ohta,et al.  An artificial retina chip made of a 128 x 128 pn-np variable-sensitivity photodetector array , 1995, IEEE Photonics Technology Letters.

[11]  Kazuo Kyuma,et al.  Artificial retina chip with a 256 x 256 array of n-MOS variable sensitivity photodetector cells , 1995, Optics East.

[12]  Andreas G. Andreou,et al.  Analog VLSI neuromorphic image acquisition and pre-processing systems , 1995, Neural Networks.

[13]  E.R. Fossum,et al.  128 Mb/s multiport CMOS binary active-pixel image sensor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[14]  M. Pasotti,et al.  B/W adaptive image grabber with analog motion vector estimator at 0.3 GOPS , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[15]  M. Yamawaki,et al.  A pixel size shrinkage of amplified MOS imager with two-line mixing , 1996 .