Direct solution of performance constraints during placement

A practical set of features for meeting the constraints of high performance designs during placement has been developed. The tool observes signal path constraints in units of time, automatically trading off delay between nets on the critical paths. The tool can observe net constraints in units of delay or capacitance. These features are based on a fast and accurate algorithm for net wiring estimation. Using a constraints method enables the true timing problem to be solved better and eliminates design iteration. Additional features specific to ECL design are also available. Results show a 52% reduction in interconnect delay versus an unconstrained placement on the first test case.<<ETX>>

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