Application of Graph Theory to Topology Generation for Logic Gates

A procedure is described which given a Boolean equation of the AOI-type will generate an area-efficient layout topology for an electronic circuit implementing this function in MOS technology. n- or p-Transistors are assumed to be arranged in two horizontal rows with their gates formed by vertical polysilicon wires crossing the cell. The topology generation problem essentially consists in interconnecting these transistors using metal wires. The proposed procedure makes use of several graphs to reflect transistor network connectivity, potential conflicts between metal wires, potential embrace situations among them, and sharing of tracks between them. Classical graph algorithms, such as colouring and critical path analysis, serve to resolve the conflicts and to assign every wire a legal location.