Compiler-Directed Energy Reduction Using Dynamic Voltage Scaling and Voltage Islands for Embedded Systems

Addressing power and energy consumption related issues early in the system design flow ensures good design and minimizes iterations for faster turnaround time. In particular, optimizations at software level, e.g., those supported by compilers, are very important for minimizing energy consumption of embedded applications. Recent research demonstrates that voltage islands provide the flexibility to reduce power by selectively shutting down the different regions of the chip and/or running the select parts of the chip at different voltage/frequency levels. As against most of the prior work on voltage islands that mainly focused on the architecture design and IP placement related issues, this paper studies the necessary software compiler support for voltage islands. Specifically, we focus on an embedded multiprocessor architecture that supports both voltage islands and control domains within these islands, and determine how an optimizing compiler can automatically map an embedded application onto this architecture. Such an automated support is critical since it is unrealistic to expect an application programmer to reach a good mapping correlating multiple factors such as performance and energy at the same time. Our experiments with the proposed compiler support show that our approach is very effective in reducing energy consumption. The experiments also show that the energy savings we achieve are consistent across a wide range of values of our major simulation parameters.

[1]  Yici Cai,et al.  Power driven placement with layout aware supply voltage assignment for voltage island generation in dual-Vdd designs , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[2]  Mahmut T. Kandemir,et al.  Exploiting inter-processor data sharing for improving behavior of multi-processor SoCs , 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

[3]  Petru Eles,et al.  Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[4]  Josep Torrellas,et al.  A Chip-Multiprocessor Architecture with Speculative Multithreading , 1999, IEEE Trans. Computers.

[5]  Michael S. Hsiao,et al.  Compiler-Directed Dynamic Frequency and Voltage Scheduling , 2000, PACS.

[6]  Mahmut T. Kandemir,et al.  Tuning data replication for improving behavior of MPSoC applications , 2004, GLSVLSI '04.

[7]  Mahmut T. Kandemir,et al.  Constraint-based Code mapping for heterogeneous Chip multiprocessors , 2005, Proceedings 2005 IEEE International SOC Conference.

[8]  Monica S. Lam,et al.  Maximizing parallelism and minimizing synchronization with affine transforms , 1997, POPL '97.

[9]  Radu Marculescu,et al.  Architecting voltage islands in core-based system-on-a-chip designs , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[10]  Seung-Moon Yoo,et al.  A semi-custom voltage-island technique and its application to high-speed serial links , 2003, ISLPED '03.

[11]  D. Marculescu,et al.  Speed and voltage selection for GALS systems based on voltage/frequency islands , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[12]  Norman P. Jouppi,et al.  CACTI 2.0: An Integrated Cache Timing and Power Model , 2002 .

[13]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[14]  M. Kandemir,et al.  Customized on-chip memories for embedded chip multiprocessors , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[15]  Martin D. F. Wong,et al.  Incremental Improvement of Voltage Assignment , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Tei-Wei Kuo,et al.  An approximation algorithm for energy-efficient scheduling on a chip multiprocessor , 2005, Design, Automation and Test in Europe.

[17]  Rajesh K. Gupta,et al.  Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[18]  Kunle Olukotun,et al.  The case for a single-chip multiprocessor , 1996, ASPLOS VII.

[19]  S. Parameswaran,et al.  Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[20]  I-Min Liu,et al.  Post-placement voltage island generation under performance requirement , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[21]  Wayne H. Wolf,et al.  Multiprocessor Systems-on-Chips , 2004, ISVLSI.

[22]  Mahmut T. Kandemir,et al.  Compiler-directed voltage scaling on communication links for reducing power consumption , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[23]  Mahmut T. Kandemir,et al.  Workload Clustering for Increasing Energy Savings on Embedded MPSoCs , 2005, Proceedings 2005 IEEE International SOC Conference.

[24]  John M. Cohn,et al.  Managing power and performance for system-on-chip designs using Voltage Islands , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[25]  Mahmut T. Kandemir,et al.  Reducing NoC energy consumption through compiler-directed channel voltage scaling , 2006, PLDI '06.

[26]  Achim Rettberg,et al.  Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture , 2006, SBCCI '06.

[27]  Mahmut T. Kandemir,et al.  Compiler Support for Voltage Islands , 2006, 2006 IEEE International SOC Conference.

[28]  Y. N. Srikant,et al.  Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture , 2008, CF '08.

[29]  Tianzhou Chen,et al.  Dynamic Compilation Framework with DVS for Reducing Energy Consumption in Embedded Processors , 2008, 2008 International Conference on Embedded Software and Systems.

[30]  Meng Wang,et al.  Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[31]  Fredrik Larsson,et al.  Simics: A Full System Simulation Platform , 2002, Computer.

[32]  Luca Benini,et al.  Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[33]  Evangeline F. Y. Young,et al.  Voltage island-driven floorplanning , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[34]  Mahmut T. Kandemir,et al.  The design and use of simplePower: a cycle-accurate energy estimation tool , 2000, Proceedings 37th Design Automation Conference.

[35]  Mahmut T. Kandemir,et al.  Optimizing array-intensive applications for on-chip multiprocessors , 2005, IEEE Transactions on Parallel and Distributed Systems.

[36]  Li Shang,et al.  Dynamic voltage scaling with links for power optimization of interconnection networks , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[37]  Steven W. K. Tjiang,et al.  SUIF: an infrastructure for research on parallelizing and optimizing compilers , 1994, SIGP.

[38]  Chau-Wen Tseng,et al.  Compiler optimizations for improving data locality , 1994, ASPLOS VI.

[39]  Li-Shiuan Peh,et al.  Dynamic power management for power optimization of interconnection networks using on/off links , 2003, 11th Symposium on High Performance Interconnects, 2003. Proceedings..