On the Reliability of Four Full Adder Cells

This study presents a top-down investigation of the reliability of four different fall adder (FA) designs. It provides insights into different parameters that affect the reliability of these FAs. The probability transfer matrix (PTM) approach is used to numerically estimate the reliability of the FAs under investigation. Simulation results show that the FAs' reliabilities depend not only on the numbers of gates, but also on the types of gates used as well as on the way these gates are interconnected. The simulation results also show how different gates affect the FAs' reliabilities and are extended with estimates from the device level. Such reliability analyses should be used for a better characterization of FA designs for future nanoelectronic technologies, in addition to the well-known speed and power consumption (which have long been used for selecting and ranking FA designs).

[1]  Massimo Alioto,et al.  Analysis and comparison on full adder block in submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Cristian Constantinescu,et al.  Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.

[3]  Jianbo Gao,et al.  Faults, error bounds and reliability of nanoelectronic circuits , 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

[4]  Sandip Tiwari,et al.  Electronics at Nanoscale: Fundamental and Practical Challenges, and Emerging Directions , 2006 .

[5]  Massimo Macucci,et al.  Critical assessment of the QCA architecture as a viable alternative to large scale integration , 2004 .

[6]  Konstantin K. Likharev,et al.  Single-electron devices and their applications , 1999, Proc. IEEE.

[7]  Hiroshi Inokawa,et al.  Binary adders of multigate single-electron transistors: specific design using pass-transistor logic , 2002 .

[8]  V. Beiu,et al.  On single-electron technology full adders , 2004, IEEE Transactions on Nanotechnology.

[9]  Andrew R. Brown,et al.  Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter , 2002 .

[10]  Yngvar Berg,et al.  A novel floating-gate multiple-valued CMOS full-adder , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[11]  Magdy Bayoumi,et al.  A novel high-performance CMOS 1-bit full-adder cell , 2000 .

[12]  Valeriu Beiu,et al.  Femto Joule Switching for Nano Electronics , 2006, IEEE International Conference on Computer Systems and Applications, 2006..

[13]  Snorre Aunet,et al.  Six subthreshold full adder cells characterized in 90 nm CMOS technology , 2006, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems.

[14]  T.S. Lande,et al.  Multifunction subthreshold gate used for a low power full adder , 2004, Proceedings Norchip Conference, 2004..

[15]  J. Hayes,et al.  Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models , 2003 .

[16]  Israel Koren.  Computer arithmetic algorithms , 1993 .

[17]  Valeriu Beiu,et al.  Gate Failures Effectively Shape Multiplexing , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[18]  John P. Hayes,et al.  Accurate reliability evaluation and enhancement via probabilistic transfer matrices , 2005, Design, Automation and Test in Europe.

[19]  P. D. Tougaw,et al.  Logical devices implemented using quantum cellular automata , 1994 .

[20]  G.A. Jullien,et al.  A method of majority logic reduction for quantum cellular automata , 2004, IEEE Transactions on Nanotechnology.

[21]  Tetsuya Asai,et al.  A majority-logic device using an irreversible single-electron box , 2003 .

[22]  Tarek Darwish,et al.  Performance analysis of low-power 1-bit CMOS full adder cells , 2002, IEEE Trans. Very Large Scale Integr. Syst..