High speed low energy CAM design using reordered overlapping

In this paper, a reordered search mechanism is introduced for high-speed low-power content-addressable memories (CAMs). Only by searching a few bits of a search word the mismatches can be occured. So to reduce the power consumption, search word circuit is partitioned into two sections that are searched sequentially. Searching will be faster if the last few bits is compared other than the rest of the bits. Each word circuit has a local control signal which controls the circuit. This allows the circuits to be operated in the required phase which greatly reduces the cycle time.

[1]  Vincent C. Gaudet,et al.  High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism , 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.

[2]  Vincent C. Gaudet,et al.  Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Hung-Yu Li,et al.  An AND-type match-line scheme for high-performance energy-efficient content addressable memories , 2006, IEEE Journal of Solid-State Circuits.

[4]  Tien-Fu Chen,et al.  An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices , 2009, IEEE Journal of Solid-State Circuits.

[5]  Ali Sheikholeslami,et al.  A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories , 2003 .

[6]  K. Pagiamtzis,et al.  A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme , 2004, IEEE Journal of Solid-State Circuits.

[7]  Jinn-Shyan Wang,et al.  An AND-type match-line scheme for high-performance energy-efficient content addressable memories , 2006 .

[8]  Chingwei Yeh,et al.  High-Speed and Low-Power Design Techniques for TCAM Macros , 2008, IEEE Journal of Solid-State Circuits.

[9]  K. Pagiamtzis,et al.  Content-addressable memory (CAM) circuits and architectures: a tutorial and survey , 2006, IEEE Journal of Solid-State Circuits.

[10]  Shoushun Chen,et al.  A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Sanghyeon Baeg Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Vincent Gripon,et al.  A low-power Content-Addressable Memory based on clustered-sparse networks , 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.