High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling /spl Delta//spl Sigma/ ADCs for broad-band applications

High-speed high-resolution /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) for broad-band communication applications must be designed at a low oversampling ratio (OSR). However, lowering the OSR limits the efficiency of a /spl Delta//spl Sigma/ ADC in achieving a high-resolution A/D conversion. This paper presents several techniques that enable the OSR reduction in /spl Delta//spl Sigma/ ADCs without compromising the resolution. 1) Noise transfer function (NTF). In this paper, a single-stage multibit /spl Delta//spl Sigma/ modulator with a high-order finite-impulse-response NTF is proposed to achieve high signal-to-quantization-noise ratios at low OSRs. Its key features include: decreased circuit complexity, improved robustness to modulator coefficient variations, and reduced sensitivity to integrator nonlinearities. Its performance is validated through behavioral simulations and compared to traditional /spl Delta//spl Sigma/ modulator structures. 2) Signal transfer function (STF). This paper describes how the STF of a /spl Delta//spl Sigma/ modulator can be designed, independently of the NTF, in order to significantly reduce the harmonic distortion due to opamp nonidealities and to help lower the power dissipation. 3) Dynamic element matching (DEM) is also presented. Data weighted averaging (DWA) has prevailed as the most practical DEM technique to linearize the internal digital-to-analog converter (DAC) of a multibit /spl Delta//spl Sigma/ modulator, especially when the number of DAC elements is large. However, the occurrence of in-band signal-dependent tones, when using DWA at a low OSR, degrades the spurious-free dynamic range. This paper proposes a simple technique, called pseudo DWA, to solve the DWA tone problem without sacrificing the signal-to-noise ratio. Its implementation adds no extra delay in the /spl Delta//spl Sigma/ feedback loop and requires only minimal additional digital hardware. Existing schemes for DWA tone reduction are also compared.

[1]  A.L. Coban,et al.  A 1.5 V 1.0 mW audio /spl Delta//spl Sigma/ modulator with 98 dB dynamic range , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[2]  R. van Veldhoven.  A tri-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[3]  L. Longo,et al.  A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio , 2000, IEEE Journal of Solid-State Circuits.

[4]  T.S. Fiez,et al.  A 14-bit current-mode /spl Sigma//spl Delta/ DAC based upon rotated data weighted averaging , 2000, IEEE Journal of Solid-State Circuits.

[5]  K. Philips,et al.  A 4.4mW 76dB complex /spl Sigma//spl Delta/ ADC for Bluetooth receivers , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[6]  Qiuting Huang,et al.  A 33mW 14b 2.5MSample/s /spl Sigma//spl Delta/ A/D converter in 0.25/spl mu/m digital CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[7]  P. Benabes,et al.  New wideband sigma-delta convertor , 1993 .

[8]  G. Temes,et al.  Wideband low-distortion delta-sigma ADC topology , 2001 .

[9]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[10]  Gabor C. Temes,et al.  Switched-capacitor DAC with analogue mismatch correction , 1999 .

[11]  Gabor C. Temes,et al.  Digital correlation technique for the estimation and correction of DAC errors in multibit mash /spl Delta//spl Sigma/ ADCs , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[12]  Craig Petrie,et al.  A background calibration technique for multibit delta-sigma modulators , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[13]  Todd L. Brooks,et al.  A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR , 1997 .

[14]  A 1.8 V 14 b /spl Delta//spl Sigma/ A/D converter with 4MSamples/s conversion , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[15]  John G. Kenney,et al.  Design of multibit noise-shaping data converters , 1993 .

[16]  Ian Galton,et al.  Simplified logic for first-order and second-order mismatch-shaping digital-to-analog converters , 2001 .

[17]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[18]  Bruce A. Wooley,et al.  A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion , 1991 .

[19]  A.A. Hamoui,et al.  A 1.8-V 3-MS/s 13-bit /spl Delta//spl Sigma/ A/D converter with pseudo data-weighted-averaging in 0.18-/spl mu/m digital CMOS , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[20]  Kenneth W. Martin,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ modulators using pseudo data-weighted averaging , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[21]  Belén Pérez-Verdú,et al.  A 13-bit, 2.2-MS/s, 55-mW multibit cascade /spl Sigma//spl Delta/ modulator in CMOS 0.7-/spl mu/m single-poly technology , 1999 .

[22]  Richard Schreier,et al.  An empirical study of high-order single-bit delta-sigma modulators , 1993 .

[23]  P. Ferguson,et al.  One bit higher order sigma-delta A/D converters , 1990, IEEE International Symposium on Circuits and Systems.

[24]  W. Sansen,et al.  A 15-b resolution 2-MHz Nyquist rate /spl Delta//spl Sigma/ ADC in a 1-/spl mu/m CMOS technology , 1998 .

[25]  Anas A. Hamoui,et al.  Delta-sigma modulator topologies for high-speed high-resolution A/D converters , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[26]  B. Leung,et al.  Some observations on tone behavior in data weighted averaging , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[27]  W. Sansen,et al.  A 3.3 V 15-bit delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL-applications , 1999, Proceedings of the 24th European Solid-State Circuits Conference.

[28]  J. Steensgaard.  Nonlinearities in SC delta-sigma A/D converters , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[29]  Joerg Hauptmann,et al.  A 13.5–bit cost optimized multi–bit delta–sigma ADC for ADSL , 1999 .

[30]  O.J.A.P. Nys,et al.  An analysis of dynamic element matching techniques in sigma-delta modulation , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[31]  Qiuting Huang,et al.  A 50-mW 14-bit 2.5-MS/s /spl Sigma/-/spl Delta/ modulator in a 0.25 /spl mu/m digital CMOS technology , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[32]  R. Baird,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .

[33]  P. van Gog,et al.  A two-channel 16/18 b audio AD/DA including filter function with 60/40 mW power consumption at 2.7 V , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[34]  Gabor C. Temes,et al.  Digital estimation and correction of DAC errors in multibit ΔΣ ADCs , 2001 .

[35]  T. Miki,et al.  14-bit 2.2-MS/s sigma-delta ADC's , 2000, IEEE Journal of Solid-State Circuits.

[36]  E. Sánchez-Sinencio,et al.  A Continuous-Time Modulator With 88-dB Dynamic Range and 1 . 1-MHz Signal Bandwidth , 2001 .

[37]  Bruce A. Wooley,et al.  A 2.5-V sigma-delta modulator for broadband communications applications , 2001 .

[38]  G. Temes,et al.  High-Speed ADC with Error Correction , 2001 .

[39]  Morteza Vadipour.  Techniques for preventing tonal behavior of data weighted averaging algorithm in σ-δ modulator , 2000 .

[40]  L. Richard Carley,et al.  CLANS: a high-level synthesis tool for high resolution data converters , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[41]  Tai-Haur Kuo,et al.  An improved technique for reducing baseband tones in sigma-delta modulators employing data weighted averaging algorithm without adding dither , 1999 .

[42]  Richard Schreier.  Mismatch-Shaping Digital-to-Analog Conversion , 1997 .

[43]  Tai-Haur Kuo,et al.  A wideband CMOS sigma-delta modulator with incremental data weighted averaging , 2002 .

[44]  C. S. Petrie,et al.  A multibit sigma-delta ADC for multimode receivers , 2003, IEEE J. Solid State Circuits.

[45]  Gabor C. Temes,et al.  Offset-compensated switched-capacitor integrators , 1990, IEEE International Symposium on Circuits and Systems.