WCET analysis for multi-core processors with shared buses and event-driven bus arbitration

Multi-core processors share common hardware resources between several processor cores. As a consequence, a program executed on one processor core may influence the execution time of the programs executed on the concurrent cores. This effect is commonly referred to as shared-resource interference. Worst-case execution time (WCET) analysis for multi-core processors has to take into account the shared-resource interference. Most existing approaches to WCET analysis for multi-core processors with shared buses and event-driven bus arbitration rely on compositionality. These approaches, however, do not support complex processor core pipelines. The existing approaches that support complex pipelines perform an exhaustive enumeration of possible interleavings of accesses to the shared bus by the different cores. Such an enumeration is infeasible in most cases. Our approach extends the state of the art in WCET analysis for single-core processors in such a way that it can deal with shared-bus interference. It does not rely on compositionality or enumeration of interleavings. Our approach calculates co-runner-insensitive WCET bounds, that are independent of the programs executed in parallel. Furthermore, it is able to improve those bounds by taking into account the bus access behavior of the concurrent cores and, thus, to calculate co-runner-sensitive WCET bounds. The implementation of our approach is evaluated for different multi-core processors. Our calculation of co-runner-insensitive WCET bounds is shown to be almost independent of the number of processor cores in terms of runtime and memory consumption. The co-runner-sensitive WCET bounds are up to 12.5% smaller than the co-runner-insensitive ones for a dual-core processor.