Light Load Efficiency Improvement in High Frequency DC-DC Buck Converter Using Dynamic Width Segmentation of Power MOSFET

This work presents a dynamic width segmentation scheme of the power MOSFETs to improve the light load efficiency in high frequency DC-DC converters. The proposed scheme first senses the load current and decides the maximum number of power MOSFET segments to be turned ON. In order to sense the load current accurately over a wide range, an improved current sensing method is also suggested. The proposed scheme is designed and simulated in a 0.5 μm Bi-CMOS technology. To validate its effectiveness, an integrated system is designed using a monolithic voltage mode, synchronous DC-DC buck converter topology switching at 20 MHz. Only the passive components (L=330 nH and C=2.2 μF) are the off-chip components. The input voltage Vin lies in the range of 2.7 V-5.5 V which is quite suitable for Li-ion or Ni-Cd battery operated applications. The output voltage is targeted at 1.2 V and maximum load current specification is 600 mA. The whole power MOSFET is segmented into 16 equal parts and a signal conditioning loop decides the number of active segments dynamically based on the load current. Simulation result shows that at the lightest load of 10 mA, the power efficiency of the converter with and without the dynamic width segmentation scheme is 40% and 19.5% respectively. This shows an efficiency improvement of nearly 103% at the lightest load of 10 mA.

[1]  P.L. Chapman,et al.  Improvement of light-load efficiency using width-switching scheme for CMOS transistors , 2005, IEEE Power Electronics Letters.

[2]  Kui Ma,et al.  A segmented output strategy for improving efficiency of DC-DC converter , 2011, 2011 International Conference on Electronics, Communications and Control (ICECC).

[3]  Aleksandar Prodic,et al.  Digitally controlled low-power DC-DC converter with segmented output stage and gate charge based instantaneous efficiency optimization , 2009, 2009 IEEE Energy Conversion Congress and Exposition.

[4]  Wai Tung Ng,et al.  A Digitally Controlled DC-DC Converter Module with a Segmented Output Stage for Optimized Efficiency , 2006, 2006 IEEE International Symposium on Power Semiconductor Devices and IC's.

[5]  Amit Patra,et al.  High-gain wideband error amplifier topology for DC-DC buck converter switching at 20 MHz , 2008 .

[6]  G.A. Rincon-Mora,et al.  Current-sensing techniques for DC-DC converters , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[7]  Amit Patra,et al.  Design of a 20 MHz DC-DC Buck Converter with 84 Percent Efficiency for Portable Applications , 2011, 2011 24th Internatioal Conference on VLSI Design.

[8]  A. A. Fomani,et al.  A segmented gate driver with adjustable driving capability for efficiency optimization , 2010, The 2010 International Power Electronics Conference - ECCE ASIA -.

[9]  Ka Nang Leung,et al.  An integrated CMOS current-sensing circuit for low-Voltage current-mode buck regulator , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.