Memory fault diagnosis by syndrome compression

In this paper we present a data compression technique that can be used to speed up the transmission of diagnosis data from the embedded RAM with built-in self-diagnosis (BISD) support. The proposed approach compresses the faulty-cell address and March syndrome to about 28% of the original size under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. The proposed compression technique reduces the time for diagnostic test, as well as the tester storage capacity requirement.

[1]  Cheng-Wen Wu,et al.  Testing content-addressable memories using functional fault modelsand march-like algorithms , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Nur A. Touba,et al.  Scan vector compression/decompression using statistical coding , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[3]  Bruce F. Cockburn,et al.  An optimal march test for locating faults in DRAMs , 1993, Records of the 1993 IEEE International Workshop on Memory Testing.

[4]  Cheng-Wen Wu,et al.  RAMSES: a fast memory fault simulator , 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

[5]  A.J. van de Goor,et al.  RAM diagnostic tests , 1996, IEEE International Workshop on Memory Technology, Design and Testing,.

[6]  Dong Sam Ha,et al.  COMPACT: a hybrid method for compressing test data , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[7]  Terry A. Welch,et al.  A Technique for High-Performance Data Compression , 1984, Computer.

[8]  Janak H. Patel,et al.  Diagnosis and Repair of Memory with Coupling Faults , 1989, IEEE Trans. Computers.

[9]  Jin-Fu Li,et al.  A built-in self-test and self-diagnosis scheme for embedded SRAM , 2000, Proceedings of the Ninth Asian Test Symposium.

[10]  Mark Rich.  A Method of Flexible Catch RAM Display for Memory Testing , 1986, ITC.

[11]  Craig Hunter,et al.  Integrated diagnostics for embedded memory built-in self test on PowerPC/sup TM/ devices , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[12]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[13]  Dong Sam Ha,et al.  An efficient method for compressing test data , 1997, Proceedings International Test Conference 1997.

[14]  Robert Gage,et al.  Hardware compression speeds on bitmap fail display , 1997, Proceedings International Test Conference 1997.

[15]  Frans P. M. Beenker,et al.  A realistic fault model and test algorithms for static random access memories , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Krishnendu Chakrabarty,et al.  Test data compression for system-on-a-chip using Golomb codes , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[17]  Nur A. Touba,et al.  Test vector decompression via cyclical scan chains and its application to testing core-based designs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[18]  Michael J. Flynn,et al.  An area model for on-chip memories and its application , 1991 .

[19]  Elizabeth M. Rudnick,et al.  Diagnostic testing of embedded memories using BIST , 2000, DATE '00.

[20]  Cheng-Wen Wu,et al.  Error catch and analysis for semiconductor memories using March tests , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).