Paradigms of connectivity for computer circuits and networks
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[1] B. Mandelbrot. Fractal Geometry of Nature , 1984 .
[2] L. Pietronero,et al. Fractals in Physics: Introductory Concepts , 1988 .
[3] I. Good,et al. Fractals: Form, Chance and Dimension , 1978 .
[4] J. Goodman,et al. Lower bound for the communication volume required for an optically interconnected array of points , 1990 .
[5] Roy L. Russo. On the Tradeoff Between Logic Performance and Circuit-to-Pin Ratio for LSI , 1972, IEEE Transactions on Computers.
[6] Charles E. Leiserson,et al. Area-Efficient VLSI Computation , 1983 .
[7] Ernest S. Kuh,et al. VLSI circuit layout : theory and design , 1985 .
[8] R.W. Keyes,et al. The evolution of digital electronics towards VLSI , 1979, IEEE Transactions on Electron Devices.
[9] M. Carpenter,et al. The Brain , 1971, Neurology.
[10] William E. Donath,et al. Placement and average interconnection lengths of computer logic , 1979 .
[11] B. Mandelbrot. THE PARETO-LEVY LAW AND THE DISTRIBUTION OF INCOME* , 1960 .
[12] W. Donath. Wire length distribution for placements of computer logic , 1981 .
[13] W. Donath. Equivalence of memory to Random Logic , 1974 .
[14] William R. Heller,et al. Prediction of wiring space requirements for LSI , 1977, DAC '77.
[15] Joseph W. Goodman,et al. The Limitations of Interconnections in Providing Communication Between an Array of Points , 1991 .
[16] Gilbert Strang,et al. Introduction to applied mathematics , 1988 .
[17] Phillip Christie,et al. Design And Simulation Of Optically Interconnected Computer Systems , 1988, Other Conferences.
[18] Joseph W. Goodman,et al. A three-dimensional optical interconnection architecture with minimal growth rate of system size , 1991 .
[19] N. H. March,et al. Order and Chaos in Nonlinear Physical Systems , 1988 .
[20] William J. Dally,et al. A VLSI Architecture for Concurrent Data Structures , 1987 .
[21] Joseph W. Goodman,et al. Comparison of system size for some optical interconnection architectures and the folded multi-facet architecture , 1991 .
[22] Haldun M. Ozaktas. A physical approach to communication limits in computation , 1992 .
[23] Jeffrey D Ullma. Computational Aspects of VLSI , 1984 .
[24] R.W. Keyes,et al. Fundamental limits in digital information processing , 1981, Proceedings of the IEEE.
[25] Michael Feuer. Connectivity of Random Logic , 1982, IEEE Transactions on Computers.
[26] Robert W. Keyes,et al. The physics of VLSI systems , 1987, Microelectronics systems design series.
[27] A. Masaki. Electrical resistance as a limiting factor for high performance computer packaging , 1989, IEEE Circuits and Devices Magazine.
[28] R. Keyes. Communication in computation , 1982 .
[29] Ivan E. Sutherland,et al. How Big Should a Printed Circuit Board Be? , 1973, IEEE Transactions on Computers.
[30] H. B. Bakoglu,et al. Circuits, interconnections, and packaging for VLSI , 1990 .
[31] Joseph W. Goodman,et al. Organization of information flow in computation for efficient utilization of high information flux communication media , 1992 .
[32] Joseph W. Goodman,et al. Multiplexed Hybrid Interconnection Architectures , 1992 .
[33] Roy L. Russo,et al. On a Pin Versus Block Relationship For Partitions of Logic Graphs , 1971, IEEE Transactions on Computers.
[34] Abbas El Gamal,et al. Two-dimensional stochastic model for interconnections in master-slice integrated circuits , 1981 .
[35] R. W. Keyes,et al. The wire-limited logic chip , 1982 .
[36] D. K. Ferry. Interconnection lengths and VLSI , 1985, IEEE Circuits and Devices Magazine.