Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization

In this paper, we present an exhaustive study on the effects of resistive-open defects in the pre-charge circuits of SRAM memories. In particular, we have analyzed the influence of resistive-opens placed in different locations of these circuits. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled with un-restored write faults (URWFs) and un-restored read faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate that the test of URWFs is more rentable in terms of resistive defect detection than that of URRFs.

[1]  Arnaud Virazel,et al.  March iC-: an improved version of March C- for ADOFs detection , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[2]  Arnaud Virazel,et al.  Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[3]  J. Otterstedt,et al.  Integration of non-classical faults in standard March tests , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).

[4]  E. S. Cooley,et al.  False write through and un-restored write electrical level fault models for SRAMs , 1997, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. NO.97TB100159).

[5]  Wayne M. Needham,et al.  High volume microprocessor test escapes, an analysis of defects our tests are missing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[6]  Arnaud Virazel,et al.  Data retention fault in SRAM memories: analysis and detection procedures , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[7]  Zaid Al-Ars,et al.  Functional memory faults: a formal notation and a taxonomy , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[8]  Arnaud Virazel,et al.  Comparison of open and resistive-open defect test conditions in SRAM address decoders , 2003, 2003 Test Symposium.

[9]  Said Hamdioui,et al.  Importance of dynamic faults for new SRAM technologies , 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..