A Novel Low Power NOR gate in SOI CMOS Technology

In this paper, a NOR gate implemented by SOI technique that eliminates power dissipation by reducing the number of parallel transistors is presented. This technique is applicable in each circuit which has parallel transistors. It can approximately decrease the area to 50% in high input circuits. In this work, we evaluate and compare the area, power and delay by the HSPICE simulator in 0.25mum CMOS technology. The simulation results show that by using the body charging of partially-depleted SOI, a NOR gate with two inputs has lower area, delay and power comparison with the complementary CMOS technology

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