Hardware Acceleration of Searchable Encryption

Searchable symmetric encryption (SSE) allows a client to outsource the storage of her data to an (untrusted) server in a private manner, while maintaining the ability to selectively search over it. A key feature of all existing SSE schemes is the tradeoff between security (in terms of the information leakage to the server) and efficiency (in terms of the operational and storage overhead on the server and client sides). The premise of this work is that SSE schemes typically offer scope for massively parallel implementations with improved efficiency without compromising security. Based on this idea, we propose a highly scalable framework for parallelized SSE implementations using hardware-based crypto-accelerators, interfaced with a software-based control unit and a memory controller unit. We choose field programmable gate arrays (FPGAs) as the platform for the crypto-accelerators due to their flexibility, reconfigurability, low time-to-market and low maintenance overheads. As a case study, we illustrate how the recently proposed SSE scheme of Lai et al. (CCS'18) may be implemented as per our framework, and the benefits thereof, including shorter preprocessing time and reduced query-response latency as compared to a software implementation.