SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-Chip

Reconfigurability is becoming an important part of System-on-Chip (SoC) design to cope with the increasing demands for simultaneous flexibility and computational power. Current hardware/software co-design methodologies provide little support for dealing with the additional design dimension introduced. Further support at the system-level is needed for the identification and modeling of dynamically re-configurable function blocks, for efficient design space exploration, partitioning and mapping, and for performance evaluation. The over-head effects, e.g. context switching and configuration data, should be included in the modeling already at the system-level in order to produce credible information for decision-making. This chapter focuses on hardware/software codesign applied for reconfigurable SoCs. We discuss exploration of additional requirements due to reconfigurability, report extensions to two C++ based languages/methodologies, SystemC and OCAPI-xl, to support those requirements, and present results of three case studies in the wireless and multimedia communication domain that were used for the validation of the approaches.

[1]  M.J. Heikkila A novel blind adaptive algorithm for channel equalization in WCDMA downlink , 2001, 12th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications. PIMRC 2001. Proceedings (Cat. No.01TH8598).

[2]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[3]  Yang Qu,et al.  Estimating the utilization of embedded FPGA co-processor , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

[4]  Jürgen Becker,et al.  Configware and morphware going mainstream , 2003, J. Syst. Archit..

[5]  Fadi J. Kurdahi,et al.  Automatic compilation to a coarse-grained reconfigurable system-opn-chip , 2003, TECS.

[6]  Juanjo Noguera,et al.  System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures , 2003, CASES '03.

[7]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[8]  Fadi J. Kurdahi,et al.  A framework for reconfigurable computing: task scheduling and context management , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Seth Copen Goldstein,et al.  PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.

[10]  Nikil D. Dutt,et al.  System-level power-performance trade-offs in bus matrix communication architecture synthesis , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[11]  Kostas Masselos,et al.  System-level modeling of dynamically reconfigurable hardware with SystemC , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[12]  Thorsten Grotker,et al.  System Design with SystemC , 2002 .

[13]  John Wawrzynek,et al.  The Garp Architecture and C Compiler , 2000, Computer.

[14]  Markus Weinhardt,et al.  From C programs to the configure-execute model , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[15]  Christophe Bobda,et al.  Synthesis of dataflow graphs for reconfigurable systems using temporal partitioning and temporal placement , 2003 .

[16]  Jeffrey H. Reed,et al.  An overview of configurable computing machines for software radio handsets , 2003, IEEE Commun. Mag..