Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core

Describes novel schemes developed to meet the demand for a reusable embedded SRAM core for application to a variety of SOC designs. PAS optimizes sense-amplifier activation timing by using the combination of a program and automatic control. MRAD minimizes timing-overhead by reducing the fluctuation of path-to-path delay. These schemes experimentally demonstrated a wide-operation range of 0.5 to 1.4 V and an access time of 600 ps.

[1]  R.V. Joshi,et al.  A 2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18 /spl mu/m CMOS bulk technology , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[2]  Kenichi Osada,et al.  Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell , 2001, IEEE J. Solid State Circuits.

[3]  M. Usami,et al.  A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).