FPGA performance versus cell granularity

An experimental approach was used to investigate the relationship between the performance of an FPGA (field-programmable gate array) and its basic cell granularity. Over a large set of design examples it was found that a four or five input cell achieves minimum average critical path delay for a wide range of programmable switch time constant, tau /sub s/. As expected, the 'optimal' cell granularity was found to increase gradually as tau /sub s/ increases.<<ETX>>

[1]  Jonathan Rose,et al.  Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency , 1990 .

[2]  Jonathan Rose,et al.  Chortle: a technology mapping program for lookup table-based field programmable gate arrays , 1990, 27th ACM/IEEE Design Automation Conference.

[3]  Giovanni De Micheli,et al.  Technology mapping using Boolean matching and don't care sets , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[4]  Sinan Kaptanoglu,et al.  Segmented channel routing , 1991, DAC '90.

[5]  Giovanni De Micheli,et al.  The Olympus synthesis system , 1990, IEEE Design & Test of Computers.

[6]  R. H. Freeman,et al.  A 9000-gate user-programmable gate array , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[7]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  A. El Gamal,et al.  An architecture for electrically configurable gate arrays , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.