On systematic illegal state identification for pseudo-functional testing

The discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of manufacturing test. Pseudo-functional testing tries to resolve this problem by identifying illegal states in functional mode and avoiding them during the test pattern generation process. Existing methods, however, can only extract a small set of illegal states in the system due to various limitations. In this paper, we first show that illegal states in the system are mainly caused by multi-fanout nets in the circuit, and we develop efficient and effective heuristics to identify them. Experimental results on benchmark circuits demonstrate the effectiveness of our proposed systematic solution.

[1]  Shlomi Sde-Paz,et al.  Frequency and Power Correlation between At-Speed Scan and Functional Tests , 2008, 2008 IEEE International Test Conference.

[2]  Mario H. Konijnenburg,et al.  Illegal state space identification for sequential circuit test generation , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[3]  Kenneth M. Butler,et al.  A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[4]  M.S. Hsiao,et al.  Mining Sequential Constraints for Pseudo-Functional Testing , 2007, 16th Asian Test Symposium (ATS 2007).

[5]  Jeff Rearick.  Too much delay fault coverage is a bad thing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[6]  Kwang-Ting Cheng,et al.  Pseudofunctional testing , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Irith Pomeranz,et al.  On generating pseudo-functional delay fault tests for scan designs , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[8]  Chung-Len Lee,et al.  Identifying invalid states for sequential circuit test generation , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Janak H. Patel,et al.  Fast identification of untestable delay faults using implications , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[10]  Kwang-Ting Cheng,et al.  Classification and identification of nonrobust untestable path delay faults , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Irith Pomeranz,et al.  Scan-Based Tests with Low Switching Activity , 2007, IEEE Design & Test of Computers.

[12]  Michael S. Hsiao,et al.  New techniques for untestable fault identification in sequential circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Janusz Rajski,et al.  Low Power Scan Shift and Capture in the EDT Environment , 2008, 2008 IEEE International Test Conference.

[14]  Yu Hu,et al.  iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing , 2008, 2008 Design, Automation and Test in Europe.

[15]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Michael S. Hsiao,et al.  A Study of Implication Based Pseudo Functional Testing , 2006, 2006 IEEE International Test Conference.

[17]  Mario H. Konijnenburg,et al.  Test pattern generation with restrictors , 1993, Proceedings of IEEE International Test Conference - (ITC).

[18]  Nilanjan Mukherjee.  Power-Aware DFT - Do we really need it? , 2008 .

[19]  Xiaoqing Wen,et al.  Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[20]  Gang Chen,et al.  Procedures for identifying untestable and redundant transition faults in synchronous sequential circuits , 2003, Proceedings 21st International Conference on Computer Design.

[21]  Daniel Brand,et al.  Identification of redundant delay faults , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Michael S. Hsiao,et al.  A novel transition fault ATPG that reduces yield loss , 2005, IEEE Design & Test of Computers.

[23]  Peter C. Maxwell,et al.  Comparing functional and structural tests , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).