Hierarchical Verification of Galois Field Circuits

This paper proposes a hierarchical method for the formal hardware verification of Galois field architecture circuits. The reduced ordered functional decision diagram has been explored. The proposed method has been found to lead to significant gains in time and space, depending on the resources that are available. The theoretical claims that were made have been supported by experiments.

[1]  Vincent Rijmen.  Efficient Implementation of the Rijndael S-box , 2000 .

[2]  Çetin Kaya Koç,et al.  Mastrovito Multiplier for General Irreducible Polynomials , 2000, IEEE Trans. Computers.

[3]  Wolfgang Rosenstiel,et al.  Efficient graph-based computation and manipulation of functional decision diagrams , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[4]  Georgi Gaydadjiev,et al.  March U: a test for unlinked memory faults , 1997 .

[5]  Yasunao Katayama,et al.  Design methodology for a one-shot Reed-Solomon encoder and decoder , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[6]  Christof Paar,et al.  Efficient Multiplier Architectures for Galois Fields GF(2 4n) , 1998, IEEE Trans. Computers.

[7]  Çetin Kaya Koç,et al.  Mastrovito Multiplier for General Irreducible Polynomials , 1999, IEEE Trans. Computers.

[8]  Kewal K. Saluja,et al.  Testing check bits at no cost in RAMs with on-chip ECC , 1993 .

[9]  Michael Nicolaidis,et al.  TRANSPARENT BIST FOR RAMS , 1992, Proceedings International Test Conference 1992.

[10]  Ad J. van de Goor,et al.  Simulation and development of short transparent tests for RAM , 2001, Proceedings 10th Asian Test Symposium.

[11]  Sungho Kang,et al.  DPSC SRAM transparent test algorithm , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[12]  N. Koblitz.  Elliptic curve cryptosystems , 1987 .

[13]  Vincent Rijmen,et al.  The Design of Rijndael , 2002, Information Security and Cryptography.

[14]  Mark G. Karpovsky,et al.  Transparent memory BIST , 1994, Proceedings of IEEE International Workshop on Memory Technology, Design, and Test.

[15]  Hans-Joachim Wunderlich,et al.  Efficient Online and Offline Testing of Embedded DRAMs , 2002, IEEE Trans. Computers.

[16]  V. N. Yarmolik,et al.  Automatic generation of symmetric transparent March memory tests , 2003, The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference..

[17]  Michael Nicolaidis,et al.  Theory of Transparent BIST for RAMs , 1996, IEEE Trans. Computers.

[18]  Rolf Drechsler,et al.  Circuit design from Kronecker Galois field decision diagrams for multiple-valued functions , 1997, Proceedings 1997 27th International Symposium on Multiple- Valued Logic.

[19]  Wen-Ben Jone,et al.  A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Wolfgang Rosenstiel,et al.  Multilevel logic synthesis based on functional decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.

[21]  Hans-Joachim Wunderlich,et al.  Error detecting refreshment for embedded DRAMs , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[22]  Bruce F. Cockburn,et al.  A transparent built-in self-test scheme for detecting single V-coupling faults in RAMs , 1994, Proceedings of IEEE International Workshop on Memory Technology, Design, and Test.

[23]  Andreas Steininger,et al.  A transparent online memory test for simultaneous detection of functional faults and soft errors in memories , 2003, IEEE Trans. Reliab..

[24]  Rolf Drechsler,et al.  AND/EXOR-based synthesis of testable KFDD-circuits with small depth , 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

[25]  Janusz Sosnowski,et al.  "In system" transparent autodiagnostics of RAMs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[26]  Hans-Joachim Wunderlich,et al.  Symmetric transparent BIST for RAMs , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[27]  Ravindra Nair.  Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories" , 1979, IEEE Trans. Computers.

[28]  R. Ramaswami,et al.  Book Review: Design and Analysis of Fault-Tolerant Digital Systems , 1990 .

[29]  Bruce F. Cockburn,et al.  Synthesized transparent BIST for detecting scrambled pattern-sensitive faults in RAMs , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[30]  Matteo Sonza Reorda,et al.  Integrating Online and Offline Testing of a Switching Memory , 1998, IEEE Des. Test Comput..

[31]  Thomas Kropf.  Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems , 1999 .

[32]  Anatolij A. Karatsuba,et al.  Multiplication of Multidigit Numbers on Automata , 1963 .

[33]  Toshiyuki Yamane,et al.  Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m) , 2001, CAV.

[34]  Thomas Kropf,et al.  Introduction to Formal Hardware Verification , 1999, Springer Berlin Heidelberg.

[35]  Rolf Drechsler,et al.  Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams , 1994, 31st Design Automation Conference.

[36]  Mark G. Karpovsky,et al.  Transparent memory testing for pattern sensitive faults , 1994, Proceedings., International Test Conference.