Efficient variable ordering heuristics for shared ROBDD

Several ordering heuristics for shared, reduced and ordered binary decision diagrams (ROBDDs) are described. These heuristics are tested on ISCAS and MCNC benchmark circuits. In all examples, the ordering is accomplished in a few seconds and generates smaller shared ROBDDs than other previously proposed heuristics. The objective is to provide a fast way to generate shared ROBDDs of reasonable sizes. The results could be used as a good initial solution to any semi-exhaustive ordering method to further reduce the sizes.<<ETX>>

[1]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[2]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[3]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[4]  Robert K. Brayton,et al.  Logic Verification Using BDDs in a Logic Synthesis Environ-ment , 1988 .

[5]  藤田 昌宏,et al.  Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams , 1988 .

[6]  Don E. Ross,et al.  Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams , 1991, 28th ACM/IEEE Design Automation Conference.

[7]  Masahiro Fujita,et al.  Evaluation and improvement of Boolean comparison method based on binary decision diagrams , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[8]  Don E. Ross,et al.  Functional approaches to generating orderings for efficient symbolic representations , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[9]  Hiroshi Sawada,et al.  Minimization of binary decision diagrams based on exchanges of variables , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[10]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[11]  Kenneth J. Supowit,et al.  Finding the Optimal Variable Ordering for Binary Decision Diagrams , 1987, 24th ACM/IEEE Design Automation Conference.

[12]  Ibrahim N. Hajj,et al.  ACCORD : Automatic Catching and Correction of Logic Design Errors in Combinational Circuits , 1992, Proceedings International Test Conference 1992.