A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters

This work presents an architecture for analog implementation of two-dimensional FIR filters. Inner filter delays are realized efficiently by means of an analog RAM, which is accumulating partial convolution products. Furthermore the structure fully exploits the filter impulse response symmetry, reducing silicon area and increasing filter phase linearity. An FIR filter for picture-in-picture applications has been designed in a 0.8 /spl mu/m CMOS technology, using the proposed architecture. According to simulation results, the system accuracy is within the 8 bit required by video applications.