Digital Adaptive Calibration of Multi-Step Analog to Digital Converters

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters Amir Zjajo1 ∗, Manuel J. Barragan2, and Jose Pineda de Gyvez3 4 1Circuits and Systems Group, Delft University of Technology, Mekelweg 4, 2628 CD, Delft, The Netherlands 2Institute of Microelectronics, University of Sevilla, Av. Americo Vespucio s/n, 41092, Sevilla, Spain 3NXP Semiconductors, High Tech Campus 32, 5656 AE, Eindhoven, The Netherlands 4Electronic Systems Group, Eindhoven University of Technology, Den Dolech 2, 5600 MB, Eindhoven, The Netherlands

[1]  A. Karanicolas,et al.  A 15-b 1-Msample/s digitally self-calibrated pipeline ADC , 1993 .

[2]  S. Hisano,et al.  A two-residue architecture for multistage ADCs , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[3]  W. Black,et al.  Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  Mikael Skoglund,et al.  A calibration scheme for imperfect quantizers , 2000, IEEE Trans. Instrum. Meas..

[5]  Jan Van der Spiegel,et al.  Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  F. O. Eynde,et al.  A high-speed CMOS comparator with 8-b resolution , 1992 .

[7]  S. Thomas Alexander,et al.  Adaptive Signal Processing , 1986, Texts and Monographs in Computer Science.

[8]  Corinna Cortes,et al.  Support-Vector Networks , 1995, Machine Learning.

[9]  Bertan Bakkaloglu,et al.  A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Masao Nakaya,et al.  An 8-bit high-speed CMOS A/D converter , 1986 .

[11]  S. P. Lloyd,et al.  Least squares quantization in PCM , 1982, IEEE Trans. Inf. Theory.

[12]  Bram Nauta,et al.  A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter , 1995 .

[13]  Amir Zjajo,et al.  An adaptive digital calibration of multi-step A/D converters , 2010, IEEE 10th INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS.

[14]  M. Nagata,et al.  On-Chip Analog Circuit Diagnosis in Systems-on-Chip Integration , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[15]  K. Lever,et al.  Improved error-table compensation of A/D converters , 1997 .

[16]  Pasquale Daponte,et al.  Influence of the architecture on ADC error modeling , 1999, IEEE Trans. Instrum. Meas..

[17]  A. Annema,et al.  A 1-V 15µW high-precision temperature switch , 2001 .

[18]  Seung-Hoon Lee,et al.  A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  G. McLachlan,et al.  The EM algorithm and extensions , 1996 .

[20]  M. Waltari,et al.  A 10-bit 200 MS/s CMOS parallel pipeline A/D converter , 2001, Proceedings of the 26th European Solid-State Circuits Conference.

[21]  Shanthi Pavan,et al.  A Dual-Mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D Converter in a 0.25- m Digital CMOS Process , 2000 .

[22]  A. Zjajo,et al.  DfT for full accessibility of multi-step analog to digital converters , 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[23]  Behzad Razavi,et al.  A 12-Bit 200-MHz CMOS ADC , 2009, IEEE Journal of Solid-State Circuits.

[24]  Mani Soma,et al.  A fault diagnosis technique for flash ADC's , 1996 .

[25]  M. Pelgrom,et al.  Monitors for a signal integrity measurement system , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[26]  Stephen H. Lewis,et al.  A 10-b 20-Msample/s analog-to-digital converter , 1992 .

[27]  P.J. Hurst,et al.  Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA , 2009, IEEE Journal of Solid-State Circuits.

[28]  Václav Hlavác,et al.  Multi-class support vector machine , 2002, Object recognition supported by user interaction for service robots.

[29]  Ian Galton,et al.  A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction , 2009, IEEE Journal of Solid-State Circuits.

[30]  John E. Dennis,et al.  Numerical methods for unconstrained optimization and nonlinear equations , 1983, Prentice Hall series in computational mathematics.

[31]  D. M. Hummels,et al.  Analog-to-digital converter error diagnosis , 1996, Quality Measurement: The Indispensable Bridge between Theory and Reality (No Measurements? No Science! Joint Conference - 1996: IEEE Instrumentation and Measurement Technology Conference and IMEKO Tec.

[32]  M. Vertregt,et al.  A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.

[33]  Raf Roovers,et al.  12-B, 60-MSample/S cascaded folding and interpolating ADC , 1999 .