Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression

One of the major challenges in testing a system-on-a-chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several test data compression techniques have been proposed. The frequency-directed run-length (FDR) code is a variable-to-variable run length code based on encoding runs of 0's. In this work, we demonstrate that higher test data compression can be achieved based on encoding both runs of 0's and 1's. We propose an extension to the FDR code and demonstrate by experimental results its effectiveness in achieving higher compression ratio.

[1]  Irith Pomeranz,et al.  Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  J.H. Patel,et al.  Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[3]  Jau-Shien Chang,et al.  Test set compaction for combinational circuits , 1992, Proceedings First Asian Test Symposium (ATS `92).

[4]  Aiman H. El-Maleh,et al.  A geometric-primitives-based compression scheme for testing systems-on-a-chip , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[5]  Krishnendu Chakrabarty,et al.  Frequency-Directed Run-Length (FDR) Codes , 2002 .

[6]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Krishnendu Chakrabarty,et al.  Test data compression for system-on-a-chip using Golomb codes , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[8]  Nur A. Touba,et al.  Test vector decompression via cyclical scan chains and its application to testing core-based designs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  R. Chandramouli,et al.  Testing systems on a chip , 1996 .

[10]  Irith Pomeranz,et al.  COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Nur A. Touba,et al.  Scan vector compression/decompression using statistical coding , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[12]  Dong Sam Ha,et al.  An efficient method for compressing test data , 1997, Proceedings International Test Conference 1997.

[13]  Nur A. Touba,et al.  Using an embedded processor for efficient deterministic testing of systems-on-a-chip , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[14]  Irith Pomeranz,et al.  Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits , 1993, 30th ACM/IEEE Design Automation Conference.

[15]  Yervant Zorian,et al.  Testing embedded-core based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).